Prevent CORE-V register to immediate normal load/stores

Added ```REG_P (XEXP (XEXP (op, 0), 1)``` to ensure
no register to immediate normal load/stores.

Issue [#61](https://github.com/openhwgroup/corev-gcc/issues/61

)

Files Changed:

  * gcc/config/riscv/corev.md: Tidy up.
  * gcc/config/riscv/riscv-protos.h: Likewise.
  * gcc/config/riscv/predicates.md: Ensure no register to
    immediate normal load/stores.
  * gcc/config/riscv/riscv.cc: Likewise.
  * gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-4.c: Added
    new test to check for illegal corev register to immediate
    load/ stores.
  * gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-4.c:
    Likewise.
  * testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c: Added commit
    to explain what was being tested for.
  * testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c: Likewise.
  * testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c: Likewise.
  * testsuite/gcc.target/riscv/cv-mem-sw-compile-1.c: Likewise.
  * testsuite/gcc.target/riscv/cv-mem-sw-compile-2.c: Likewise.
  * testsuite/gcc.target/riscv/cv-mem-sw-compile-3.c: Likewise.

Signed-off-by: Mary Bennett <mary.bennett@embecosm.com>