Commit 8fc41a33 authored by NandniJamnadas's avatar NandniJamnadas Committed by Nandni Jamnadas
Browse files

CV32E40Pv2 Update Post Increment Load/Store



    Removed redundant instructions for all CORE-V Post Increment Load/Store
    as this duplicates RISC-V Load/Store instructions.

    * opcodes/riscv-opc.c: Removed redundant CORE-V Post Increment
      Load/Store instructions.
    * gas/testsuite/gas/riscv/cv-mem-lb.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lb.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lbu.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lbu.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lh.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lh.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lhu.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lhu.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lw.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-lw.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sb.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sb.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sh.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sh.s: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sw.d: deleted.
    * gas/testsuite/gas/riscv/cv-mem-sw.s: deleted.

Signed-off-by: default avatarNandni Jamnadas <nandni.jamnadas@embecosm.com>
parent 228784c0
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment