Added support for CORE-V hardware loop

Added two relocations REL12 and RELU5, the CORE-V INSN_CLASSes, the MATCH
and MASKs and the hardware loop instructions.

bfd/ChangeLog:

	* bfd-in2.h: REGENERATED.
	* elfnn-riscv.c: Add relocations for CORE-V hardware loop.
	* elfxx-riscv.c: Add relocations and amend howto lookup.
	* riscv.c: Add BFD_RELOC_RISCV_CVPCREL_UI12 and
	BFD_RELOC_RISCV_CVPCREL_URS1.

gas/ChangeLog:

	* config/tc-riscv.c: Add CORE-V harware loop support.
	* config/tc-riscv.h: Likewise.
	* doc/c-riscv.texi: Note Xcvhwlp as additional ISA extension
	for CORE-V.