Added support for CORE-V hardware loop

Added two relocations REL12 and RELU5, the CORE-V INSN_CLASSes, the MATCH
and MASKs and the hardware loop instructions.

bfd/ChangeLog:

	* bfd-in2.h: Added CORE-V hardware loop specific relocations.
	* elfnn-riscv.c: Added relocations for CORE-V hardware loop.
	* elfxx-riscv.c: Added relocations and amend howto lookup.
	* riscv.c: Added BFD_RELOC_RISCV_CVPCREL_UI12 and
	BFD_RELOC_RISCV_CVPCREL_URS1.

gas/ChangeLog:

	* config/tc-riscv.c: Added CORE-V harware loop support.
	* config/tc-riscv.h: Likewise.
	* doc/c-riscv.texi: Noted Xcorev as additional ISA extension
	for CORE-V.

gas/testsuite/ChangeLog:

	* gas/riscv/cv-hwloop-01.d: Added new test.
	* gas/riscv/cv-hwloop-01.l: Likewise.
	* gas/riscv/cv-hwloop-01.s: Likewise.
	* gas/riscv/cv-hwloop-02.d: Likewise.
	* gas/riscv/cv-hwloop-02.l: Likewise.
	* gas/riscv/cv-hwloop-02.s: Likewise.
	* gas/riscv/cv-hwloop-03.d: Likewise.
	* gas/riscv/cv-hwloop-03.l: Likewise.
	* gas/riscv/cv-hwloop-03.s: Likewise.
	* gas/riscv/cv-hwloop-04.d: Likewise.
	* gas/riscv/cv-hwloop-04.l: Likewise.
	* gas/riscv/cv-hwloop-04.s: Likewise.
	* gas/riscv/cv-hwloop-05.d: Likewise.
	* gas/riscv/cv-hwloop-05.l: Likewise.
	* gas/riscv/cv-hwloop-05.s: Likewise.
	* gas/riscv/cv-hwloop-06.d: Likewise.
	* gas/riscv/cv-hwloop-06.l: Likewise.
	* gas/riscv/cv-hwloop-06.s: Likewise.
	* gas/riscv/cv-hwloop-07.d: Likewise.
	* gas/riscv/cv-hwloop-07.l: Likewise.
	* gas/riscv/cv-hwloop-07.s: Likewise.
	* gas/riscv/cv-hwloop-08.d: Likewise.
	* gas/riscv/cv-hwloop-08.l: Likewise.
	* gas/riscv/cv-hwloop-08.s: Likewise.
	* gas/riscv/cv-hwloop-count.d: Likewise.
	* gas/riscv/cv-hwloop-count.s: Likewise.
	* gas/riscv/cv-hwloop-counti.d: Likewise.
	* gas/riscv/cv-hwloop-counti.s: Likewise.
	* gas/riscv/cv-hwloop-endi.d: Likewise.
	* gas/riscv/cv-hwloop-endi.s: Likewise.
	* gas/riscv/cv-hwloop-setup.d: Likewise.
	* gas/riscv/cv-hwloop-setup.s: Likewise.
	* gas/riscv/cv-hwloop-setupi.d: Likewise.
	* gas/riscv/cv-hwloop-setupi.s: Likewise.
	* gas/riscv/cv-hwloop-starti.d: Likewise.
	* gas/riscv/cv-hwloop-starti.s: Likewise.
	* gas/riscv/cv-hwloop-09.d: Likewise.
	* gas/riscv/cv-hwloop-09.l: Likewise.
	* gas/riscv/cv-hwloop-09.s: Likewise.
	* gas/riscv/cv-hwloop-10.d: Likewise.
	* gas/riscv/cv-hwloop-10.l: Likewise.
	* gas/riscv/cv-hwloop-10.s: Likewise.

include/ChangeLog:

	* elf/riscv.h: Added CORE-V hardware loop specific relocations.
	* opcode/riscv.h: Added CORE-V hardware loop specific masks and
	CORE-V instruction class. Added macros for unsigned I type
	immediate and loop number.

ld/ChangeLog:

	* emultempl/riscvelf.em: Added initial CORE-V support.

ld/testsuite/ChangeLog:

	* ld-riscv-elf/ld-riscv-elf.exp: Added CORE-V hardware loop
	  tests.
	* ld-riscv-elf/cv-hwloop-starti.s: Added new test.
	* ld-riscv-elf/cv-hwloop-starti.d: Likewise.
	* ld-riscv-elf/cv-hwloop-endi.d: Likewise.
	* ld-riscv-elf/cv-hwloop-endi.s: Likewise.
	* ld-riscv-elf/cv-hwloop-setup.d: Likewise.
	* ld-riscv-elf/cv-hwloop-setup.s: Likewise.
	* ld-riscv-elf/cv-hwloop-setupi.d: Likewise.
	* ld-riscv-elf/cv-hwloop-setupi.s: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c: Added CORE-V hardware loop support.
	* riscv-opc.c: Likewise.

Signed-off-by: Mary Bennett <mary.bennett@embecosm.com>