PULP: Added Event Load Instructions + Tests Version 1.0.0 extension in assembler

       The event load instruction cv.elw is only supported if the
       PULP_CLUSTER parameter is set to 1. The event load performs a
       load word and can cause the CV32E41P to enter a sleep state

        bfd/
            * elfxx-riscv.c: (riscv_multi_subset_supports): Added
              INSN_CLASS_XCOREVELW.
            * elfxx-riscv.c: (riscv_multi_subset_supports_ext): Likewise.

        gas/
            * testsuite/gas/riscv/cv-elw-pass.d: Added supported instruction
              test.
            * testsuite/gas/riscv/cv-elw-pass.s: Likewise.
            * testsuite/gas/riscv/cv-elw-fail.d: Added unsupported
              instruction test.
            * testsuite/gas/riscv/cv-elw-fail.s: Likewise.
            * testsuite/gas/riscv/cv-elw-pass.l: Likewise.

        include/
            * opcode/riscv-opc.h: Added corresponding MATCH and MASK
              instruction opcode macros.
            * opcode/riscv-opc.h: Added corresponding DECLARE_INSN.
            * opcode/riscv.h: (riscv_insn_class) Added
              INSN_CLASS_COREV_ELW.

        opcodes/
            * riscv-opc.c: (riscv_opcode) Added event load
            instructions.

Signed-off-by: NandniJamnadas <nandni.jamnadas@embecosm.com>