- Apr 05, 2021
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Antony Pavlov authored
Signed-off-by:Antony Pavlov <antonynpavlov@gmail.com>
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Antony Pavlov authored
import wb_sdram_ctrl-r4.core from https://github.com/fusesoc/fusesoc-cores/ fusesoc-cores commit: > commit 466508116da7d3734c82b6c5fd2dd0e6af1407c4 > Author: Olof Kindgren <olof.kindgren@gmail.com> > Date: Fri Oct 19 21:43:17 2018 +0200 > > Add wb_sdram_ctrl 0-r4 Signed-off-by: -
Antony Pavlov authored
import uart16550-1.5.5-r1.core from https://github.com/fusesoc/fusesoc-cores/ fusesoc-cores commit: > commit ff26b9a93cfd764b119977ad004ca57a1cb44c7e > Author: Olof Kindgren <olof.kindgren@gmail.com> > Date: Mon Mar 5 22:10:43 2018 +0100 > > Add uart16550 1.5.5-r1 Signed-off-by:
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Antony Pavlov authored
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Antony Pavlov authored
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- Apr 04, 2021
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
openocd TIP: > --- a/tcl/fpga/altera-ep3c10.cfg > +++ b/tcl/fpga/altera-ep3c10.cfg > @@ -1,4 +1,5 @@ > # Altera Cyclone III EP3C10 > # see Cyclone III Device Handbook, Volume 1; > # Table 14–5. 32-Bit Cyclone III Device IDCODE > -jtag newtap ep3c10 tap -expected-id 0x020f10dd -irlen 10 > +#jtag newtap ep3c10 tap -expected-id 0x020f10dd -irlen 10 > +jtag newtap ep4 tap -expected-id 0x020f70dd -irlen 10 openocd -f tcl/interface/altera-usb-blaster.cfg -f tcl/fpga/altera-ep3c10.cfg -c init -c "svf -tap ep4.tap /tmp/1.svf" -c shutdown Also see https://github.com/Goshik92/FFTVisualizer/blob/master/Verilog/FFTVisualisator.qsf Signed-off-by:
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Antony Pavlov authored
Here is fusesoc-1.8.4 error message: fusesoc --cores-root cores/ sim picorv32-wb-soc ... INFO: Preparing ::mt48lc16m16a2:0 INFO: Downloading... ERROR: Setup failed : Failed to download 'http://www.micron.com/~/media/Documents/Products/Sim%20Model/DRAM/DRAM/4012mt48lc16m16a2.zip '. 'Page not found' Signed-off-by:
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- Jun 10, 2018
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Antony Pavlov authored
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- Apr 17, 2018
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Antony Pavlov authored
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- Apr 15, 2018
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Antony Pavlov authored
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Antony Pavlov authored
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- Jan 25, 2018
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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- Jan 23, 2018
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Antony Pavlov authored
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- Jan 22, 2018
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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- Jan 16, 2018
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Antony Pavlov authored
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- Jan 15, 2018
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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- Jan 08, 2018
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Antony Pavlov authored
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- Jan 06, 2018
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
See http://www.waveshare.com/wiki/CoreEP2C5 for board details. Signed-off-by:
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
wb_ram works incorrectly on Cyclone II, e.g.: nmon> w 40000000 12345678 nmon> d 40000000 78000000 See Cyclone II FPGA Family Errata, needed for dual-port dual-clock mode M4K http://www.altera.com/support/kdb/solutions/fb27180.html Using altsyncram in single port operation mode fixes the problem. Signed-off-by:
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- Jan 05, 2018
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
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Antony Pavlov authored
Add c10lp-evkit and core-ep4ce6 boards. Use Quartus 17.1. Signed-off-by: -
Antony Pavlov authored
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Antony Pavlov authored
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