- Jan 09, 2022
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Craig Topper authored
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Florian Hahn authored
Update the check lines in 2 existing tests to use patterns + variables to match some IR to make them independent of value naming.
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Craig Topper authored
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Craig Topper authored
Previously this was documented as having the behavior of the "target's native float-to-int conversion". After D115804, clang uses saturating FP cast intrinsics which have the same behavior on all targets. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D116856
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Mehdi Amini authored
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Mehdi Amini authored
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Kazu Hirata authored
Identified with readability-redundant-member-init.
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Kazu Hirata authored
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Kazu Hirata authored
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Kazu Hirata authored
Identified with bugprone-argument-comment.
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Philip Reames authored
Goal is to remove use of isOpNewLike. I looked at a couple approaches to this, and this turned out to be the cheapest one. Just letting deref_or_null be generated causes a bunch of test diffs, and I couldn't convince myself there wasn't a real regression somewhere. A generic instcombine to convert deref_or_null + nonnull to deref is annoying complicated since you have to mix facts from callsite and declaration while manipulating only existing call site attributes. It just wasn't worth the code complexity. Note that the change in new-delete-itanium.ll is a real regression. If you have a callsite which overrides the builtin status of a nobuiltin declaration, *and* you don't put the apppriate attributes on that callsite, you may lose the deref fact. I decided this didn't matter; if anyone disagrees, you can add this case to the generic non-null inference.
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Arthur O'Dwyer authored
The reason for those nested namespaces is explained in D115315: > AIUI, this keeps the CPO's own type from ADL'ing into the `std::ranges` > namespace; e.g. `foobar(std::ranges::uninitialized_default_construct)` > should not consider `std::ranges::foobar` a candidate, even if > `std::ranges::foobar` is not a CPO itself. Also, of course, consistency > (Chesterton's Fence, the economist's hundred-dollar bill): if it were > safe to omit the namespace, we'd certainly want to do it everywhere, > not just here. This makes these three niebloids more consistent with the other Ranges niebloids we've already implemented, such as the `ranges::begin` group and the `ranges::uninitialized_default_construct` group. FWIW, we still have three different indentation-and-comment styles among these three groups. Differential Revision: https://reviews.llvm.org/D116569
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Dave Lee authored
Ensure that errors in `frame variable` are reflected in result object. The statistics for `frame variable` show invocations as being successful, even when executing one of the error paths. This change replaces `result.GetErrorStream()` with `result.AppendError()`, which also sets the status to `eReturnStatusFailed`. Differential Revision: https://reviews.llvm.org/D116788
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Simon Pilgrim authored
[CGObjCMac] Use castAs<> instead of getAs<> to avoid dereference of nullptr inside BuildRCBlockVarRecordLayout This will assert the cast is correct instead of returning nullptr (UnionType is a subtype of RecordType so this should be clean).
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- Jan 08, 2022
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Florian Hahn authored
Checking the full output provides more context and makes it easier to review changes to the test in a follow-up patch.
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Florian Hahn authored
Replace a uses of undef in the tests. The undef causes runtime checks to be trivially fold/removeable, which does defeat the purpose of the test.
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Florian Hahn authored
Replace some uses of undef in the tests. The undef causes runtime checks to be trivially fold/removeable, which does defeat the purpose of the tests.
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Simon Pilgrim authored
To enable this on all targets there's still a number of regressions due to getSplatValue/getTargetVShiftNode but these don't really affect pre-AVX targets.
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Simon Pilgrim authored
More closely matches the documentation Requested by @nikic
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Simon Pilgrim authored
This will assert the cast is correct instead of returning nullptr
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Simon Pilgrim authored
We're testing that the RegionLoop pointer is null in the first part of the check, so we need to check that its non-null before dereferencing it in a later part of the check.
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Simon Pilgrim authored
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Simon Pilgrim authored
This is very similar to the existing ROTL/ROTR support for scalar shifts in LowerRotate, I think as time goes on we should be able to share much of this code in helpers between Funnel Shift + Rotation lowering.
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Uday Bondhugula authored
Fix crash in the presence of yield values. Multiple fixes to affine loop tiling pre-condition checks and return status. Do not signal pass failure on a failure to tile since the IR is still valid. Detect index set computation failure in checkIfHyperrectangular and return failure. Replace assertions with proper status return. Move checks to an appropriate place earlier in the utility before mutation happens. Differential Revision: https://reviews.llvm.org/D116738
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Florian Hahn authored
Unsigned compares of the form <u 0 are always false. Do not create such a redundant check in generateOverflowCheck. The patch introduces a new lambda to create the check, so we can exit early conveniently and skip creating some instructions feeding the check. I am planning to sink a few additional instructions as follow-ups, but I would prefer to do this separately, to keep the changes and diff smaller. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D116811
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Groverkss authored
This patch moves PresburgerSet to Presburger/ directory. This patch is purely mechincal, it only moves and renames functionality and tests. This patch is part of a series of patches to move presburger functionality to Presburger/ directory. Reviewed By: arjunp Differential Revision: https://reviews.llvm.org/D116836
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Jay Foad authored
Change CombinerHelper::matchBitfieldExtractFromShrAnd to use getPreferredShiftAmountTy for the shift-amount-like operands of G_UBFX just like all the other G_[SU]BFX combines do. This better matches the AMDGPU legality rules for these instructions. Differential Revision: https://reviews.llvm.org/D116803
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Jay Foad authored
1. Fix CombinerHelper::matchBitfieldExtractFromAnd to check legality with the correct types for the G_UBFX that it builds. 2. Fix AMDGPUTargetLowering::isConstantUnsignedBitfieldExtractLegal to match the legality rules: result and first operand can be s32 or s64 but the "shift amount" operands are always s32. 3. Add AMDGPU tests where the post-legalizer combiner would create illegal MIR without the above fixes. Differential Revision: https://reviews.llvm.org/D116802
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Christian Sigg authored
- Prevent symbols from being stripped so that it can run with 'RelWithDebInfo'. - Adjust llvm-support CHECKs after code changes. - Polish mlir-support CHECKs as suggested in https://reviews.llvm.org/D116646. Differential Revision: https://reviews.llvm.org/D116837
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Lang Hames authored
This should fix the build failure at https://lab.llvm.org/buildbot/#/builders/165/builds/12997
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Lang Hames authored
Inspired by LLVM_DEBUG, but using environment variables rather than command line options. Code can use ORC_RT_DEBUG(...) (if ORC_RT_DEBUG_TYPE is set), or ORC_RT_DEBUG_WITH_TYPE(<type>, ...) (if ORC_RT_DEBUG_TYPE is not set. E.g. in headers). Debug logging is enabled in the executor by setting the ORC_RT_DEBUG environment variable. Debug logging can be restricted by type by setting the ORC_RT_DEBUG_TYPES environment variable to a comma separated list of types, e.g. ORC_RT_DEBUG_TYPES=macho_platform,sps. Differential Revision: https://reviews.llvm.org/D116139
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Lang Hames authored
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Lang Hames authored
These types performed identical roles. Merging them simplifies interoperability between JITLink and ORC APIs (allowing us to address a few FIXMEs).
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Kazu Hirata authored
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owenca authored
Differential Revision: https://reviews.llvm.org/D116318
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Tanya Lattner authored
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Craig Topper authored
By default we return the width of an LMUL=1 register. We can enable testing with larger LMUL values by returning a larger bit width. This patch adds a RISCV specific option to provide a LMUL which will be multiplied by the LMUL=1 bit width. Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D116339
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Kazu Hirata authored
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Kito Cheng authored
getMinVectorRegisterBitWidth means what vector types is supported in this target, and actually RISC-V support all fixed length vector types with vector length less than `getMinRVVVectorSizeInBits`, so set it to 16, means 2 x i8, that is minimal fixed length vector size in theory. That also fixed one issue, some testcase migth become non-vectorizable when `-riscv-v-vector-bits-min` set to larger value, because the vector size is smaller than `-riscv-v-vector-bits-min`. For example, following code can vectorize by SLP with `-riscv-v-vector-bits-min=128` or `-riscv-v-vector-bits-min=256`, but can't vectorize `-riscv-v-vector-bits-min=512` or larger: ``` void foo(double *da) { da[0] = 0; da[1] = 1; da[2] = 2; da[3] = 3; } ``` Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D116534
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