- Dec 28, 2020
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Nikita Popov authored
If neon is disabled, LowerCTPOP will return SDValue() to indicate that normal legalization should be used. However, ReplaceNodeResults does not check for this and pushes the empty SDValue() onto the result vector, which will subsequently result in a crash. Differential Revision: https://reviews.llvm.org/D93825
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- Dec 27, 2020
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David Green authored
This cleans up and regenerates the NEON addw/addl/subw/subl/mlal etc tests, adding some tests that turn the zext into anyextend using an and mask.
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David Green authored
This cleans up and regenerates the NEON addw/addl/subw/subl/mlal etc tests, adding some tests that turn the zext into anyextend using an and mask.
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Pavel Labath authored
The tests don't work with remote debugservers. This isn't a problem with any particular test, but the test infrastructure itself, which is why each of these tests has a @skipIfDarwinEmbedded decorator. This patch replaces that with a central category-based solution. It also moves the ad-hoc windows skipping mechanism there too.
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Pavel Labath authored
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Amara Emerson authored
[GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from getConstantVRegVal" landed. APInt binary ops don't promote types but instead assert, which a combine was relying on.
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Craig Topper authored
I guess I missed this in 4252f777 when I modified most patterns.
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Craig Topper authored
We weren't consistently marking unary instructions as OneInput and vid.v is really ZeroInput but we had no way to mark that. This patch improves this by removing the error prone OneInput constraint. Instead we just always look for the mask in the last operand. It appears that the "CheckReg" variable used for the check on the broken instruction was unitialized or garbage because it was also used for VS1/VS2 constraints. I've scoped the variable locally to each check now. I've gone through and set NoConstraint on instructions that don't have a real VMConstraint and don't have a mask as the last operand. I've also removed the unused enum values in RISCVBaseInfo.h. We never use them in C++ and we have separate versions in a td file. Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D93784
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Chris Lattner authored
Implement Bug 46698, making ODS synthesize a getType() method that returns a specific C++ class for OneResult methods where we know that class. This eliminates a common source of casts in things like: myOp.getType().cast<FIRRTLType>().getPassive() because we know that myOp always returns a FIRRTLType. This also encourages op authors to type their results more tightly (which is also good for verification). I chose to implement this by splitting the OneResult trait into itself plus a OneTypedResult trait, given that many things are using `hasTrait<OneResult>` to conditionalize various logic. While this changes makes many many ops get more specific getType() results, it is generally drop-in compatible with the previous behavior because 'x.cast<T>()' is allowed when x is already known to be a T. The one exception to this is that we need declarations of the types used by ops, which is why a couple headers needed additional #includes. I updated a few things in tree to remove the now-redundant `.cast<>`'s, but there are probably many more than can be removed. Differential Revision: https://reviews.llvm.org/D93790
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Arthur Eubanks authored
These all have NPM RUN lines.
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Nikita Popov authored
This tests their handling inside LVI. See D93065 for wider context.
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Kazu Hirata authored
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Kazu Hirata authored
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Kazu Hirata authored
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Nathan James authored
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Sanjay Patel authored
I am hoping to extend the reduction matching code, and it is hard to distinguish "ReductionData" from "ReducedValueData". So extend the tree/root metaphor to include leaves. Another problem is that the name "OperationData" does not provide insight into its purpose. I'm not sure if we can alter that underlying data structure to make the code clearer.
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- Dec 26, 2020
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Sanjay Patel authored
This will get more complicated when we handle intrinsics like maxnum.
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mydeveloperday authored
[clang-format] PR48569 clang-format fails to align case label with `switch` with Whitesmith Indentation https://bugs.llvm.org/show_bug.cgi?id=48569 This is a tentative fix which addresses a PR raise regarding Case indentation when working with Whitesmiths Indentation I could not find online any reference sources as to what the case indentation for Whitesmith's should be (or be allowed to be) But according to the documentation, we don't obey the rules for Whitesmith's ``` In particular, the documentation states that this option is to "indent case labels one level from the switch statement. When false, use the same indentation level as for the switch statement." ``` The behaviour we add here is actually as the TODO in the tests used to state in {D67627}, but when {D82016} was added and I brought these tests out from being TODO I realized I changed the indentation. Reviewed By: curdeius, HazardyKnusperkeks Differential Revision: https://reviews.llvm.org/D93806
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Nikita Popov authored
In 35676a4f I've added handling for non-trivial dominating conditions that imply non-zero on the true branch. This adds the same support for the false branch. The changes in pr45360.ll change block ordering and naming, but don't change the control flow. The urem is still guaraded by a non-zero check correctly.
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Nikita Popov authored
Add tests for non-trivial conditions that imply non-zero on the false branch rather than the true branch. The last case already folds due to canonicalization.
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Monk Chiang authored
Define vwredsumu/vwredsum/vfwredosum/vfwredsum We work with @rogfer01 from BSC to come out this patch. Authored-by:
Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by:
Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D93807
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Kazu Hirata authored
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Kazu Hirata authored
The last use of the function was removed on Sep 29, 2010 in commit 99c985c3.
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Nikita Popov authored
This allows us to handle assumes etc in the recursive isKnownNonZero() checks.
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Kazu Hirata authored
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- Dec 25, 2020
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Nikita Popov authored
The dominating condition handling in isKnownNonZero() currently only takes into account conditions of the form "x != 0" or "x == 0". However, there are plenty of other conditions that imply non-zero, a common one being "x s> 0". Peculiarly, the handling for assumes was already dealing with more general non-zero-ness conditions, so this just reuses the same logic for the dominating condition case.
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Nikita Popov authored
Check conditions that imply non-zero, even if they are not literally "x != 0". Using ctlz for testing, as explicit comparison might get folded by other reasoning.
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Nikita Popov authored
This allows us to handle additional cases like assumes.
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Nikita Popov authored
D71264 started using a context instruction in a computeKnownBits() call. However, if aliasing between two GEPs is checked, then the choice of context instruction will be different for alias(GEP1, GEP2) and alias(GEP2, GEP1), which is not supposed to happen. Resolve this by remembering which GEP a certain VarIndex belongs to, and use that as the context instruction. This makes the choice of context instruction predictable and symmetric. It should be noted that this choice of context instruction is non-optimal (just like the previous choice): The AA query result is only valid at points that are reachable from *both* instructions. Using either one of them is conservatively correct, but a larger context may also be valid to use. Differential Revision: https://reviews.llvm.org/D93183
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Eugene Zhulenev authored
Depends On D93592 Add support for `async.execute` async value unwrapping operands: ``` %token = async.execute(%async_value as %unwrapped : !async.value<!my.type>) { ... async.yield } ``` Reviewed By: csigg Differential Revision: https://reviews.llvm.org/D93598 -
Eugene Zhulenev authored
1. Add new methods to Async runtime API to support yielding async values 2. Add lowering from `async.yield` with value payload to the new runtime API calls `async.value` lowering requires that payload type is convertible to LLVM and supported by `llvm.mlir.cast` (DialectCast) operation. Reviewed By: csigg Differential Revision: https://reviews.llvm.org/D93592
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Praveen authored
OpenMP 4.5 - Variables that appear in expressions for statement function definitions may not appear in OpenMP Private, Firstprivate or Lastprivate clauses. Test case : omp-private03.f90 Reviewed By: kiranchandramohan Differential Revision: https://reviews.llvm.org/D93213 -
Georgii Rymar authored
This is similar to D93760. When something is wrong with the hash table header we dump its context as a raw data. Currently we have the calculation overflow issue and it is possible to bypass the validation we have (and crash). The patch fixes it. Differential revision: https://reviews.llvm.org/D93799
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Georgii Rymar authored
It was discussed in D92545 that we might want to improve messages reported when something is wrong with the stack size section. This patch does it. Differential revision: https://reviews.llvm.org/D93802
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Georgii Rymar authored
This allows to get rid of lots for typedefs/usings from many places. Differential revision: https://reviews.llvm.org/D93801
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Amara Emerson authored
No test for this because it's a CSE verifier failure that's only exposed in a WIP patch for enabling CSE throughout the AArch64 GISel pipeline.
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Zakk Chen authored
Define vpopc/vfirst intrinsics and lower to V instructions. We work with @rogfer01 from BSC to come out this patch. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D93795
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Kazu Hirata authored
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Zakk Chen authored
Define vector mask-register logical intrinsics and lower them to V instructions. Also define pseudo instructions vmmv.m and vmnot.m. We work with @rogfer01 from BSC to come out this patch. Authored-by:
Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by:
Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D93705
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ShihPo Hung authored
This patch defines vrgather intrinsics and lower to V instructions. We work with @rogfer01 from BSC to come out this patch. Authored-by:
Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by:
ShihPo Hung <shihpo.hung@sifive.com> Differential revision: https://reviews.llvm.org/D93797
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