This simplifies the test case added in e399dd60 to only require indvars
and simple-loop-unswitch. This allows adding the test case for #58158 to
the same file, keeping related tests together.

This reverts commit 36a20020.

This patch introduces a new AArch64 ISD node (OBSCURE_COPY) that can
be used when we want to prevent SVE object address calculations
from being rematerialised between a smstop/smstart and a call.
At the moment we use COPY to copy the frame index to a register,
which leads to problems because the "simple register coalescing"
pass understands the COPY instruction and attempts to rematerialise
an address calculation with 'addvl' between an smstop and a call.
When in streaming mode the 'addvl' instruction may have different
behaviour because the streaming SVE vector length is not guaranteed
to equal the normal SVE vector length.

The new ISD opcode OBSCURE_COPY gets lowered to a new pseudo
instruction also called OBSCURE_COPY. This ensures it cannot be
rematerialised and we expand this into a simple move very late in
the machine instruction pipeline.

A new test is added here:

CodeGen/AArch64/sme-streaming-interface.ll

Differential Revision: https://reviews.llvm.org/D134940

This patch update the fir::isUnlimitedPolymorphicType function
to reflect the chosen design. It adds also a fir::isPolymorphicType
function.

Reviewed By: jeanPerier

Differential Revision: https://reviews.llvm.org/D135143

This makes sure that the instructions of the prologue matches the
SEH opcodes.

Also remove a couple redundant cases of setting HasWinCFI; it was
already set unconditionally after the conditional cases.

Differential Revision: https://reviews.llvm.org/D135101

These fields are guarded elsewhere, but were missing here.

Reviewed By: wallace

Differential Revision: https://reviews.llvm.org/D133778

Differential Revision: https://reviews.llvm.org/D135151

Differential Revision: https://reviews.llvm.org/D135161

Context: https://discourse.llvm.org/t/psa-retire-linalg-filter-based-patterns/63785

Depends on D135200

Differential Revision: https://reviews.llvm.org/D135222

When trying to debug some `compiler-rt` unittests, I initially had a hard
time because

- even in a `Debug` build one needs to set `COMPILER_RT_DEBUG` to get
  debugging info for some of the code and
- even so the unittests used a hardcoded `-O2` which often makes debugging
  impossible.

This patch addresses this by instead using `-O0` if `COMPILER_RT_DEBUG`.
Two tests in `sanitizer_type_traits_test.cpp` need to be disabled since
they have undefined references to `__sanitizer::integral_constant<bool,
true>::value`.

Tested on `sparcv9-sun-solaris2.11`, `amd64-pc-solaris2.11`, and
`x86_64-pc-linux-gnu`.

Differential Revision: https://reviews.llvm.org/D91620

Context: https://discourse.llvm.org/t/psa-retire-linalg-filter-based-patterns/63785

Differential Revision: https://reviews.llvm.org/D135200

We often have constraints for array attributes that they are sorted
non-decreasing or strictly increasing. This change adds AttrConstraint classes
that support DenseArrayAttr for integer types.

Differential Revision: https://reviews.llvm.org/D134944

Reviewed By: lntue, michaelrj

Differential Revision: https://reviews.llvm.org/D135225

Following a precedent set in D46861.

These intrinsics are simply expanded to regular icmp/fcmp instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121594

The `readability-braces-around-statements` check tries to look at the
closing parens of the if condition to determine where to insert braces,
however, "consteval if" statements don't have a condition, and always
have braces regardless, so the skip can be checked.

The `readability-simplify-boolean-expr` check looks at the condition
of the if statement to determine what could be simplified, but as
"consteval if" statements do not have a condition that could be
simplified, they can also be skipped here.

There may still be more checks that try to look at the conditions of
`if`s that aren't included here

Fixes https://github.com/llvm/llvm-project/issues/57568

Reviewed By: njames93, aaron.ballman

Differential Revision: https://reviews.llvm.org/D133413

Reviewed By: MatzeB, arsenm
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D109213

If we have thread states, the program is going to be rather slow. If we
don't, we want to avoid wasting shared memory. This patch introduces a
slight penalty (malloc + indirection) for the slow path and reduces
resource usage for the fast path.

Differential Revision: https://reviews.llvm.org/D135037

We should use OpenMP atomics but they don't take variable orderings.
Maybe we should expose all of this in the header but that solves only
part of the problem anyway.

Differential Revision: https://reviews.llvm.org/D135036

Also fixes one ordering argument not used.

Differential Revision: https://reviews.llvm.org/D135035

The pointer comparison was causing confusion for capture tracking, let's
avoid confusion.

Differential Revision: https://reviews.llvm.org/D135160

Differential Revision: https://reviews.llvm.org/D135172

The patch selects VSELECT_VL/VP_MERGE_VL that uses VF(N)M(ACC|SAC) as its
true operand and the adden of the true operand as its false operand.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D135080

This is primarily used for Arm64EC, but it could be used for other
non-standard calling conventions. The testcase is based on an Arm64EC
thunk generated by MSVC.

The name save_any_reg comes from Microsoft documentation, but the full
encoding isn't specified there; this is reverse-engineered from the
behavior of the unwinder. (Thanks to Martin Storsjö for his example of
how to write simple unwinder testcases by directly calling
RtlVirtualUnwind.)

Differential Revision: https://reviews.llvm.org/D135196

The allocation hints for copies of ACC registers assumed that we would only be
copying between VSRp and UACC registers. In reality it is also possible to copy
between UACC and ACC registers.

This patch adds a new case for the ACC copy to fix that issue.
Note that the test case added with this patch will hit an assert without the
fix.

Reviewed By: lei, amyk

Differential Revision: https://reviews.llvm.org/D134501

Fixes #58062.

Differential Revision: https://reviews.llvm.org/D135026

This change moves the pass from the Linalg dialect to the bufferization dialect.

Differential Revision: https://reviews.llvm.org/D135130

(Re-Apply with fixes to clang MicrosoftMangle.cpp)

This is a first step towards high level representation for fp8 types
that have been built in to hardware with near term roadmaps. Like the
BFLOAT16 type, the family of fp8 types are inspired by IEEE-754 binary
floating point formats but, due to the size limits, have been tweaked in
various ways in order to maximally use the range/precision in various
scenarios. The list of variants is small/finite and bounded by real
hardware.

This patch introduces the E5M2 FP8 format as proposed by Nvidia, ARM,
and Intel in the paper: https://arxiv.org/pdf/2209.05433.pdf

As the more conformant of the two implemented datatypes, we are plumbing
it through LLVM's APFloat type and MLIR's type system first as a
template. It will be followed by the range optimized E4M3 FP8 format
described in the paper. Since that format deviates further from the
IEEE-754 norms, it may require more debate and implementation
complexity.

Give...

Once we are in the `Unreachable` we want to disable type checking, but
we were unconditionally returning `true` here which means we encountered
and error.  Instead we unconditionally return false to signal no error.

Fixes: https://github.com/llvm/llvm-project/issues/56935

Differential Revision: https://reviews.llvm.org/D135195

Doing so allows G_SEXT_INREG to be combined away for many vector cases.

Differential Revision: https://reviews.llvm.org/D135168

As a result of making these legal, and tweaking the combine to allow vectors,
we generate vector G_SEXT_INREG during legalization.

The reason we want to make these legal in the first place is to allow for
more combine opportunities. Once those have been done, we can just lower them
back to shifts in the post-legalizer lowering.

This needs to be one commit otherwise we start causing tests to fail due to
incomplete support for selection etc.

Add the -fpass-plugin option to flang which dynamically loads LLVM passes from the
shared object passed as the argument to the flag. The behavior of the option is
designed to replicate that of the same option in clang and thus has the same
capabilities and limitations.

- Multiple instances of -fpass-plugin=path-to-file can be specified and each of the
  files will be loaded in that order.

- The flag can be passed to both flang-new and flang-new -fc1.

Differential Revision: https://reviews.llvm.org/D129156

This information is not preserved in MIR today. So this patch adds
information to RISCVMachineFunctionInfo when the vreg is created for
the argument.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D134621

Now they're only included at all if the mode is fullbuild.

Differential Revision: https://reviews.llvm.org/D135221

Add the macro CPU_COUNT as well as a backing function to implement the
functionality.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D135179

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D135181

This matches ld64 behavior

Differential Revision: https://reviews.llvm.org/D135082

Let's see if it's been fixed by my recent ABI fixes...