Wrong error message is fixed and a note of argument is printed.

Tests are added in `llvm/test/TableGen/template-args.td`.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D156966

Backwards frame index elimination uses backwards register scavenging,
which is preferred because it does not rely on accurate kill flags.

Differential Revision: https://reviews.llvm.org/D156691

[X86] combineAnd - limit and(extract_vector_elt(shuffle(x)) -> extract_vector_elt(shuffle'(x)) fold to one use of the extract_vector_elt.

Prevents a regression in an upcoming patch.

[X86] LowerBuildVectorv16i8 - attempt to merge lowest 2 x i16 insertions into a i32 MOVD scalar_to_vectpr

Similar to D156350, if we were going to create 2 x i16 insertions (MOVD+PINSRW), try to merge them into a single MOVD to reduce the amount of GPR<->VEC traffic

InterpState frees resources in the destructor but doesn't
have user-written copy c'tor or assignment operator, so copying it using
default ones can cause double free.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D156900

An 'arith.constant dense<0>' is currently lowered to 'arm_sme.zero' as
part of the 'vector.transfer_write' lowering during '-vector-to-arm-sme'
conversion. This patch makes this lowering independent of the
'vector.transfer_write'. This can then be extended for further tile
types and non-zero constants.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D156802

IdDeclInfoMap frees resources in the destructor but doesn't
have user-written copy c'tor or assignment operator, so copying it using
default ones can cause double free.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D156904

This patch extends the ArmSME load and store op lowering to use the
memref indices. An integration test that loads two 32-bit element ZA
tiles from memory and stores them back to memory in reverse order to
verify this is added.

Depends on D156467 D156558

Reviewed By: awarzynski, dcaballe

Differential Revision: https://reviews.llvm.org/D156689

This patch does a few things:
  1. Add a new type called Undefined to ScalarTypeKind.
  2. Make RVVType::applyModifier early return when encounter invalid
     ScalarType, otherwise it could be modified to "non-invalid" type in the following code.
  3. When FixedLMULType::SmallerThan is applied, the lmul should be "<" than
     specified one, so lmuls which are ">=" should be marked as invalid.

Differential Revision: https://reviews.llvm.org/D156223

This revision uses std::array instead of normal c arrays to store the
operand and result segment sizes. This is a follow up to
https://reviews.llvm.org/D155919, which converted the operand and result
segment sizes to properties. Its use of c arrays triggered warnings in
downstream projects due to the direct comparison of c arrays. This
revision fixes the warnings using std::arrays that implement a
proper comparison operator, which compares the array elements rather
that the array pointers.

Note: it seems the comparison operator is effectively dead code for now.
It still seems useful to fix the warning and ensure the comparison works
as expected assume someone starts using it at some point in time.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D156888

Solaris 12 was re-christened as Solaris 11.4 while still in beta, so all
references are long obsolete and can be removed.

Tested on `amd64-pc-solaris2.11`.

Differential Revision: https://reviews.llvm.org/D156861

This commit adds a DIModuleAttr to the set of debug info attributes and
extends the LLVM IR import and export to support it.

DIModule metadata is missing in the LLVM LangRef and cannot be produced
from C or C++ input. So far, we only observed classic flang producing
such DI metadata.

Reviewed By: zero9178

Differential Revision: https://reviews.llvm.org/D156969

Regarding this NFC change, please refer to the discussion in this thread. https://reviews.llvm.org/D150851#4467261

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D155786

It has been added in extractelt-int-rv32.ll.

Since D156363 this test has been failing with -Wmissing-multilib if
multilib is configured for the BareMetal toolchain.
By setting sysroot the test is more hermetic and the failure is avoided.

The declaration was added without a corresponding function definition
by:

  commit c181f21a
  Author: Andrzej Warzynski <andrzej.warzynski@arm.com>
  Date:   Wed Oct 19 17:04:31 2022 +0000

If we do not have exlusion blocks and the target is live, we only need
to reach a dominating block.

If we cannot reach the target from the entry of a function without
exclusion set, we cannot reach it at all. This can allow us to filter
unique queries based on a uniform one.

After 28a91473 we don't use
eliminateInstrViaWidening with InvertCondition = false. Therefore all
related code is dead.

Reviewed By: DaniilSuchkov

Differential Revision: https://reviews.llvm.org/D156908

`build()` guarantees that we'll always have a `Decl`, so we can simplify the code.

Reviewed By: ymandel, xazax.hun

Differential Revision: https://reviews.llvm.org/D156859

Previously we used the number of registers needed saved and pushable as the
number of pushed registers. We also use pushed register number to caculate
the stack size. It is not correct because Zcmp pushes registers from $ra to the
max register needed saved and there is no gurantee that the needed saved
registers are a sequenced list from $ra.

There is an example about that. PushPopRegs should be 6 (ra,s0 - s4)= instead of 1.
```
; llc -mtriple=riscv32 -mattr=+zcmp
define void @foo() {
entry:
; Old:    .cfi_def_cfa_offset 16
; New:    .cfi_def_cfa_offset 32
  tail call void asm sideeffect "li s4, 0", "~{s4}"()
  ret void
}
```

Reviewed By: Jim, kito-cheng

Differential Revision: https://reviews.llvm.org/D156407

This reverts commit 30b11b0e.

We've found and fixed another failing test.

Reviewed By: Caslyn

Differential Revision: https://reviews.llvm.org/D156938

Leaving this field unitialized could led to crashes when it'll diverge from the
IRNumbering phase.

Differential Revision: https://reviews.llvm.org/D156965

This doesn't bring us to parity with the test/CodeGen/RISCV/half-* test
cases, it simply picks off an initial set that can be supported
especially easy. In order to make the review more manageable, I'll
follow up with other cases.

There is zero innovation in the test cases - they simply take the
existing half/float cases and replace f16->bf16 and half->bfloat.

Differential Revision: https://reviews.llvm.org/D156895

No new lits are added since addToFrontier is only used in MachineDominanceFrontier::addToFrontier.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D155417

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D155863

Fixes #64229.

Differential Revision: https://reviews.llvm.org/D156655

The refactored template can now be used with MachineVerifier.

Resubmitted after fixing build errors:

- Shared libraries build failed with undefined references due to "extern
  template" declarations.
- Modules build failed due to a cycle dependence between llvm/ADT and llvm/IR.
  The Generic*Impl.h files should be in llvm/IR to prevent this.

Differential Revision: https://reviews.llvm.org/D156522

This restores commit 93a37067.
Originally reverted in 466bd998.

isOperationLegalOrCustomOrPromote returns true only if VT is other or legal
and operation action is Legal, Custom or Promote.
Permit a vector binary operation can be converted to scalar binary operation which is custom lowered with illegal type.
One of cases is i32 isn't a legal type on RV64 and its ALU operations is set to custom lowering,
so vadd for element type i32 can be converted to addw.

Reviewed By: jacquesguan, craig.topper

Differential Revision: https://reviews.llvm.org/D156692

Delay consuming tokens until we are certain that the next token is not top
level block. Otherwise we bail out as if we saw an @end for better diagnostic
and recovery.

Fixes https://github.com/llvm/llvm-project/issues/64065.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D156277.

Enforce the following restriction specified in 2.13
A var may appear at most once in all the clauses of declare directives for a
function, subroutine, program, or module.

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D156945

Lower the deviceptr clause for the OpenACC declare directive.

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D156828

This change exposes the reversebits library function for HLSL, excluding floating point types.
The reversebits function is supported for all scalar, vector, and matrix types.

The full documentation of the HLSL reversebits function is available here:
https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/reversebits

Reviewed By: python3kgae

Differential Revision: https://reviews.llvm.org/D156933