- Dec 06, 2022
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Sergey Kachkov authored
Support reading of VLENB (vector byte length) control register, that can be required for correct unwinding of RVV objects on stack. Differential Revision: https://reviews.llvm.org/D136264
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Nikita Popov authored
This is not NFC because the DSE BatchAA is more powerful than the default one due to EarliestEscape CaptureInfo, so this might improve results in some cases.
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Jean Perier authored
When generating character assignment operations, the generic code generates some code to handle truncation and padding when the length differ at runtime. A bypass already exists when the length are compile time constant and match, but it was not used for the trivial case where the RHS and LHS length is the same SSA value. In such case, even though, the length is not know at compile time, it is known to be the same. This will simplify the code creating character temporaries from a variable in HLFIR that will use this assignment code. Note that this probably has little impact on performance (llvm may be clever enough to later catch that for us). But it makes the generated IR a lot more readable at little cost. Differential Revision: https://reviews.llvm.org/D139330
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Valery Pykhtin authored
[AMDGPU] Fix GCNSubtarget::getMinNumVGPRs, add unit test to check consistency between GCNSubtarget's getMinNumVGPRs, getMaxNumVGPRs and getOccupancyWithNumVGPRs. ``` /// \returns Minimum number of VGPRs that meets given number of waves per /// execution unit requirement supported by the subtarget. unsigned getMinNumVGPRs(unsigned WavesPerEU) const; /// \returns Maximum number of VGPRs that meets given number of waves per /// execution unit requirement supported by the subtarget. unsigned getMaxNumVGPRs(unsigned WavesPerEU) const; /// Return the maximum number of waves per SIMD for kernels using \p VGPRs /// VGPRs unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const; ``` While working on RP tracking issues I noticed that getMinNumVGPRs return incorrect values: the problem is large VGPR granule sizes on GFX10+ architectures. Some of the occupancies aren't reachable because require the same amount of VGPR granules as others. For example 19 waves occupancy on gfx1010 require the same amount of granules as 20 waves so the resultng occupancy would be 20. SGPRs have the same issue and even have inconsistency between getMaxNumSGPRs and getOccupancyWithNumSGPRs. It will be addressed in the next patch. Legend: # MinVGPR and MaxVGPR are values returned by getMinNumVGPRs and getMaxNumVGPRs for a given Occ. # (ONumber) is the value returned by getOccupancyWithNumVGPRs for a given MinVGPR or MaxVGPR. # R means range problem: MinVGPR should be less than MaxVGPR and both should refer to the same occupancy. Unit test output without the fix: ``` ./build/unittests/Target/AMDGPU/AMDGPUTests --gtest_filter=AMDGPU.TestVGPRLimitsPerOccupancy --print-cpu-reg-limits gfx90a gfx940: Occ MinVGPR MaxVGPR 8 0 (O8) 64 (O8) 7 65 (O7) 72 (O7) 6 73 (O6) 80 (O6) 5 81 (O5) 96 (O5) 4 97 (O4) 128 (O4) 3 129 (O3) 168 (O3) 2 169 (O2) 256 (O2) 1 257 (O1) 512 (O1) gfx600 gfx600 gfx601 gfx601 gfx601 gfx602 gfx602 gfx602 gfx700 gfx700 gfx701 gfx701 gfx702 gfx703 gfx703 gfx703 gfx704 gfx704 gfx705 gfx801 gfx801 gfx802 gfx802 gfx802 gfx803 gfx803 gfx803 gfx803 gfx805 gfx805 gfx810 gfx810 gfx900 gfx902 gfx904 gfx906 gfx908 gfx909 gfx90c: Occ MinVGPR MaxVGPR 10 0 (O10) 24 (O10) 9 25 (O9) 28 (O9) 8 29 (O8) 32 (O8) 7 33 (O7) 36 (O7) 6 37 (O6) 40 (O6) 5 41 (O5) 48 (O5) 4 49 (O4) 64 (O4) 3 65 (O3) 84 (O3) 2 85 (O2) 128 (O2) 1 129 (O1) 256 (O1) gfx1030w64 gfx1031w64 gfx1032w64 gfx1033w64 gfx1034w64 gfx1035w64 gfx1036w64 gfx1102w64 gfx1103w64: Occ MinVGPR MaxVGPR 16 0 (O16) 32 (O16) 15 33 (O12) R 32 (O16) 14 33 (O12) R 32 (O16) 13 33 (O12) R 32 (O16) 12 33 (O12) 40 (O12) 11 41 (O10) R 40 (O12) 10 41 (O10) 48 (O10) 9 49 (O9) 56 (O9) 8 57 (O8) 64 (O8) 7 65 (O7) 72 (O7) 6 73 (O6) 80 (O6) 5 81 (O5) 96 (O5) 4 97 (O4) 128 (O4) 3 129 (O3) 168 (O3) 2 169 (O2) 256 (O2) 1 256 (O2) R 256 (O2) gfx1100w64 gfx1101w64: Occ MinVGPR MaxVGPR 16 0 (O16) 48 (O16) 15 49 (O12) R 48 (O16) 14 49 (O12) R 48 (O16) 13 49 (O12) R 48 (O16) 12 49 (O12) 60 (O12) 11 61 (O10) R 60 (O12) 10 61 (O10) 72 (O10) 9 73 (O9) 84 (O9) 8 85 (O8) 96 (O8) 7 97 (O7) 108 (O7) 6 109 (O6) 120 (O6) 5 121 (O5) 144 (O5) 4 145 (O4) 192 (O4) 3 193 (O3) 252 (O3) 2 253 (O2) 256 (O2) 1 256 (O2) R 256 (O2) gfx1030w32 gfx1031w32 gfx1032w32 gfx1033w32 gfx1034w32 gfx1035w32 gfx1036w32 gfx1102w32 gfx1103w32: Occ MinVGPR MaxVGPR 16 0 (O16) 64 (O16) 15 65 (O12) R 64 (O16) 14 65 (O12) R 64 (O16) 13 65 (O12) R 64 (O16) 12 65 (O12) 80 (O12) 11 81 (O10) R 80 (O12) 10 81 (O10) 96 (O10) 9 97 (O9) 112 (O9) 8 113 (O8) 128 (O8) 7 129 (O7) 144 (O7) 6 145 (O6) 160 (O6) 5 161 (O5) 192 (O5) 4 193 (O4) 256 (O4) 3 256 (O4) R 256 (O4) 2 256 (O4) R 256 (O4) 1 256 (O4) R 256 (O4) gfx1100w32 gfx1101w32: Occ MinVGPR MaxVGPR 16 0 (O16) 96 (O16) 15 97 (O12) R 96 (O16) 14 97 (O12) R 96 (O16) 13 97 (O12) R 96 (O16) 12 97 (O12) 120 (O12) 11 121 (O10) R 120 (O12) 10 121 (O10) 144 (O10) 9 145 (O9) 168 (O9) 8 169 (O8) 192 (O8) 7 193 (O7) 216 (O7) 6 217 (O6) 240 (O6) 5 241 (O5) 256 (O5) 4 256 (O5) R 256 (O5) 3 256 (O5) R 256 (O5) 2 256 (O5) R 256 (O5) 1 256 (O5) R 256 (O5) gfx1010w64 gfx1011w64 gfx1012w64 gfx1013w64: Occ MinVGPR MaxVGPR 20 0 (O20) 24 (O20) 19 25 (O18) R 24 (O20) 18 25 (O18) 28 (O18) 17 29 (O16) R 28 (O18) 16 29 (O16) 32 (O16) 15 33 (O14) R 32 (O16) 14 33 (O14) 36 (O14) 13 37 (O12) R 36 (O14) 12 37 (O12) 40 (O12) 11 41 (O11) 44 (O11) 10 45 (O10) 48 (O10) 9 49 (O9) 56 (O9) 8 57 (O8) 64 (O8) 7 65 (O7) 72 (O7) 6 73 (O6) 84 (O6) 5 85 (O5) 100 (O5) 4 101 (O4) 128 (O4) 3 129 (O3) 168 (O3) 2 169 (O2) 256 (O2) 1 256 (O2) R 256 (O2) gfx1010w32 gfx1011w32 gfx1012w32 gfx1013w32: Occ MinVGPR MaxVGPR 20 0 (O20) 48 (O20) 19 49 (O18) R 48 (O20) 18 49 (O18) 56 (O18) 17 57 (O16) R 56 (O18) 16 57 (O16) 64 (O16) 15 65 (O14) R 64 (O16) 14 65 (O14) 72 (O14) 13 73 (O12) R 72 (O14) 12 73 (O12) 80 (O12) 11 81 (O11) 88 (O11) 10 89 (O10) 96 (O10) 9 97 (O9) 112 (O9) 8 113 (O8) 128 (O8) 7 129 (O7) 144 (O7) 6 145 (O6) 168 (O6) 5 169 (O5) 200 (O5) 4 201 (O4) 256 (O4) 3 256 (O4) R 256 (O4) 2 256 (O4) R 256 (O4) 1 256 (O4) R 256 (O4) ``` After the fix: ``` gfx90a gfx940: Occ MinVGPR MaxVGPR 8 0 (O8) 64 (O8) 7 65 (O7) 72 (O7) 6 73 (O6) 80 (O6) 5 81 (O5) 96 (O5) 4 97 (O4) 128 (O4) 3 129 (O3) 168 (O3) 2 169 (O2) 256 (O2) 1 257 (O1) 512 (O1) gfx600 gfx600 gfx601 gfx601 gfx601 gfx602 gfx602 gfx602 gfx700 gfx700 gfx701 gfx701 gfx702 gfx703 gfx703 gfx703 gfx704 gfx704 gfx705 gfx801 gfx801 gfx802 gfx802 gfx802 gfx803 gfx803 gfx803 gfx803 gfx805 gfx805 gfx810 gfx810 gfx900 gfx902 gfx904 gfx906 gfx908 gfx909 gfx90c: Occ MinVGPR MaxVGPR 10 0 (O10) 24 (O10) 9 25 (O9) 28 (O9) 8 29 (O8) 32 (O8) 7 33 (O7) 36 (O7) 6 37 (O6) 40 (O6) 5 41 (O5) 48 (O5) 4 49 (O4) 64 (O4) 3 65 (O3) 84 (O3) 2 85 (O2) 128 (O2) 1 129 (O1) 256 (O1) gfx1030w64 gfx1031w64 gfx1032w64 gfx1033w64 gfx1034w64 gfx1035w64 gfx1036w64 gfx1102w64 gfx1103w64: Occ MinVGPR MaxVGPR 16 0 (O16) 32 (O16) 15 0 (O16) 32 (O16) 14 0 (O16) 32 (O16) 13 0 (O16) 32 (O16) 12 33 (O12) 40 (O12) 11 33 (O12) 40 (O12) 10 41 (O10) 48 (O10) 9 49 (O9) 56 (O9) 8 57 (O8) 64 (O8) 7 65 (O7) 72 (O7) 6 73 (O6) 80 (O6) 5 81 (O5) 96 (O5) 4 97 (O4) 128 (O4) 3 129 (O3) 168 (O3) 2 169 (O2) 256 (O2) 1 169 (O2) 256 (O2) gfx1100w64 gfx1101w64: Occ MinVGPR MaxVGPR 16 0 (O16) 48 (O16) 15 0 (O16) 48 (O16) 14 0 (O16) 48 (O16) 13 0 (O16) 48 (O16) 12 49 (O12) 60 (O12) 11 49 (O12) 60 (O12) 10 61 (O10) 72 (O10) 9 73 (O9) 84 (O9) 8 85 (O8) 96 (O8) 7 97 (O7) 108 (O7) 6 109 (O6) 120 (O6) 5 121 (O5) 144 (O5) 4 145 (O4) 192 (O4) 3 193 (O3) 252 (O3) 2 253 (O2) 256 (O2) 1 253 (O2) 256 (O2) gfx1030w32 gfx1031w32 gfx1032w32 gfx1033w32 gfx1034w32 gfx1035w32 gfx1036w32 gfx1102w32 gfx1103w32: Occ MinVGPR MaxVGPR 16 0 (O16) 64 (O16) 15 0 (O16) 64 (O16) 14 0 (O16) 64 (O16) 13 0 (O16) 64 (O16) 12 65 (O12) 80 (O12) 11 65 (O12) 80 (O12) 10 81 (O10) 96 (O10) 9 97 (O9) 112 (O9) 8 113 (O8) 128 (O8) 7 129 (O7) 144 (O7) 6 145 (O6) 160 (O6) 5 161 (O5) 192 (O5) 4 193 (O4) 256 (O4) 3 193 (O4) 256 (O4) 2 193 (O4) 256 (O4) 1 193 (O4) 256 (O4) gfx1100w32 gfx1101w32: Occ MinVGPR MaxVGPR 16 0 (O16) 96 (O16) 15 0 (O16) 96 (O16) 14 0 (O16) 96 (O16) 13 0 (O16) 96 (O16) 12 97 (O12) 120 (O12) 11 97 (O12) 120 (O12) 10 121 (O10) 144 (O10) 9 145 (O9) 168 (O9) 8 169 (O8) 192 (O8) 7 193 (O7) 216 (O7) 6 217 (O6) 240 (O6) 5 241 (O5) 256 (O5) 4 241 (O5) 256 (O5) 3 241 (O5) 256 (O5) 2 241 (O5) 256 (O5) 1 241 (O5) 256 (O5) gfx1010w64 gfx1011w64 gfx1012w64 gfx1013w64: Occ MinVGPR MaxVGPR 20 0 (O20) 24 (O20) 19 0 (O20) 24 (O20) 18 25 (O18) 28 (O18) 17 25 (O18) 28 (O18) 16 29 (O16) 32 (O16) 15 29 (O16) 32 (O16) 14 33 (O14) 36 (O14) 13 33 (O14) 36 (O14) 12 37 (O12) 40 (O12) 11 41 (O11) 44 (O11) 10 45 (O10) 48 (O10) 9 49 (O9) 56 (O9) 8 57 (O8) 64 (O8) 7 65 (O7) 72 (O7) 6 73 (O6) 84 (O6) 5 85 (O5) 100 (O5) 4 101 (O4) 128 (O4) 3 129 (O3) 168 (O3) 2 169 (O2) 256 (O2) 1 169 (O2) 256 (O2) gfx1010w32 gfx1011w32 gfx1012w32 gfx1013w32: Occ MinVGPR MaxVGPR 20 0 (O20) 48 (O20) 19 0 (O20) 48 (O20) 18 49 (O18) 56 (O18) 17 49 (O18) 56 (O18) 16 57 (O16) 64 (O16) 15 57 (O16) 64 (O16) 14 65 (O14) 72 (O14) 13 65 (O14) 72 (O14) 12 73 (O12) 80 (O12) 11 81 (O11) 88 (O11) 10 89 (O10) 96 (O10) 9 97 (O9) 112 (O9) 8 113 (O8) 128 (O8) 7 129 (O7) 144 (O7) 6 145 (O6) 168 (O6) 5 169 (O5) 200 (O5) 4 201 (O4) 256 (O4) 3 201 (O4) 256 (O4) 2 201 (O4) 256 (O4) 1 201 (O4) 256 (O4) ``` Reviewed By: #amdgpu, arsenm Differential Revision: https://reviews.llvm.org/D138443
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Vladislav Khmelevsky authored
Use container's reverse iterators Differential Revision: https://reviews.llvm.org/D139335
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Diego Caballero authored
This patch adds `replaceAllUsesExcept` to the rewriter class. The implementation is copy-pasted from Value + calling `updateRootInPlace` to notify the listeners about the corresponding IR changes. Reviewed By: Mogball Differential Revision: https://reviews.llvm.org/D139382
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Nikita Popov authored
While MemorySSA use optimization was already using BatchAA, the publicly exposed MSSA walkers were using plain AAResults. This is not great, because it is expected that clobber walking will make repeated AA queries. This patch makes the clobber API accept a BatchAAResults instance. The plain APIs are kept as wrappers and will create a BatchAAResults instance for the duration of the query. In the future, the explicit BatchAAResults arguments will be used to share AA results across queries, not just within one query. Differential Revision: https://reviews.llvm.org/D136164
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dbakunevich authored
Fixed a bug that the "re" library was used in this python file, but there was no import of it. Differential Revision: https://reviews.llvm.org/D137926
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Fangrui Song authored
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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jacquesguan authored
Reviewed By: reames Differential Revision: https://reviews.llvm.org/D135534
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Mark Lacey authored
It seems unnecessarily limiting to disallow recursive partial inlining, and there are clearly cases where it can benefit code by avoiding a function call and potentially enabling other transformations like dead argument elimination in cases where an argument is only used prior to the early-out test at the top of the function. The pass already properly rewrites the recursive calls within the body of the freshly cloned function, so the only change here is removing the bail-out when recursion is detected. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D136383
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Vitaly Buka authored
Msan needs noundef consistency between interface and implementation. If we call C++ from C we can have noundef on C++ side, and no noundef on caller C side, noundef implementation will not set TLS for return value, no noundef caller will expect it. Then we have false reports in msan. The workaround could be set TLS to zero even for noundef return values. However if we do that always it will increase binary size by about 10%. If we do that selectively we need to handle "address is taken" functions, any non local functions, and probably all function which have musttail callers. Which is still a lot. The existing implementation of HasStrictReturn refers to C standard as the reason not enforcing noundef. I believe it applies only to the case when return statement is omitted. Testing on Google codebase I never see such cases, however I've see tens of cases where C code returns actual uninitialized variables, but we ignore that it because of "omitted return" case. So this patch will: 1. fix false-positives with TLS missmatch. 2. detect bugs returning uninitialized variables for C as well. 3. report "omitted return" cases stricter than C, which is already a warning and very likely a bug in a code anyway. Reviewed By: kda Differential Revision: https://reviews.llvm.org/D139296
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Kazu Hirata authored
SMLoc uses std::nullopt_t, so it should include optional rather than None.h.
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Ramkumar Ramachandra authored
Since tosa.pad is lowered strictly to artih and tensor ops, move ConvertPad from TosaToLinalg to TosaToTensor, benefitting non-Linalg Tosa targets. TensorToLinalg exists, and is trivial, so nothing is lost. Signed-off-by:
Ramkumar Ramachandra <r@artagnon.com> Differential Revision: https://reviews.llvm.org/D139091
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Kazu Hirata authored
This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Kazu Hirata authored
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
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Kazu Hirata authored
These .cpp files do not use llvm::None anymore. Since these are not header files, we can remove them pretty safely without deprecating them first.
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Jeff Niu authored
The pass was not checking for uninitialized states due to dead code. This patch also makes LLVMFuncOp correctly return a null body when it is external. Fixes #58807 Depends on D139388 Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D139389
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Jeff Niu authored
Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D139388
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jacquesguan authored
This patch implements shouldFoldSelectWithIdentityConstant for RISCV. It would try to generate vmerge after the binary instruction and let them folded to maksed instruction later. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D131551
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Jeff Niu authored
Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D139372
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Freddy Ye authored
Reviewed By: mgehre-amd Differential Revision: https://reviews.llvm.org/D139170
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Nawrin Sultana authored
Differential Revision: https://reviews.llvm.org/D139376
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Matt Arsenault authored
This was added in 29e2d946 and likely never worked in a useful way. The test added for it fails when converted to opaque pointers, since the lifetime intrinsic now directly uses the address. The code was only trying to handle a user indirectly through a bitcast instruction. That would never have been useful; a bitcast of a global value would be folded to a ConstantExpr cast. I also don't understand why it was special casing use_empty on the cast. Relax the check to be either BitCastOperator or AddrSpaceCastOperator. In practice, BitCastOperator won't appear today. I believe the change in parallel_deletion_cg_update is a correct improvement but I didn't fully follow it. .omp_outlined..0 is used in a constant expression cast to a call which ends up getting deleted.
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jacquesguan authored
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D131950
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Michael Buch authored
On Windows rebuilding the binary isn't enough to unload it on progrem restart. But the assumption of the test is that on program re-run LLDB destroys and replaces the old module with the newly built version. One will have to try hard to evict the module from the ModuleList (possibly including a call to `SBDebugger::MemoryPressureDetected`. See D138724
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Guilhem authored
Implicit cast between char* and StringRef when writing sections. Reproduce: ``` $> llvm-objcopy --dump-section=name=name.data out.wasm $> llvm-objcopy --remove-section=name out.wasm out_no_name.wasm $> llvm-objcopy --add-section=name=name.data out_no_name.wasm out_new_name.wasm ``` Reviewed By: dschuff Differential Revision: https://reviews.llvm.org/D139210
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Stella Laurenzo authored
At import time, these calls to `logging.debug()` implicitly call `logging.basicConfig` (https://docs.python.org/3/library/logging.html#logging.basicConfig), setting logging config for the whole project which cannot then be overwritten later. For instance, consider the following test script: ``` import logging import jax logger = logging.getLogger(__name__) logging.basicConfig(level=logging.INFO) logger.info('info') ``` This should log out `'info'`, but because when `import jax` is called, this `_mlir_lib/__init__.py` file is run and a `logging.debug` is called, calling `logging.basicConfig`, my `logging.basicConfig(level=logging.INFO)` does nothing. Fix: instead of using root logger, use a module level logger. Found in this issue: https://github.com/google/jax/issues/12526 Reviewed By: stellaraccident Differential Revision: https://reviews.llvm.org/D134812
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Roman Lebedev authored
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David Blaikie authored
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ChunyuLiao authored
D135833, lowerSelect: (select C, -1/0, X) -> or/and Keep (select c, 0/-1, X), thus making better use of lowerSelect to eliminate branch instructions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139272
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Stella Stamenova authored
Revert "[mlir][sparse] Refactoring: abstract sparse tensor memory scheme into a SparseTensorDescriptor class." This reverts commit 8a7e69d1. This broke the windows mlir buildbot: https://lab.llvm.org/buildbot/#/builders/13/builds/29257
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wren romano authored
This change cleans up the conversion pass re the "dim"-vs-"lvl" and "sizes"-vs-"shape" distinctions of the runtime. A quick synopsis includes: * Adds new `SparseTensorStorageBase::getDimSize` method, with `sparseDimSize` wrapper in SparseTensorRuntime.h, and `genDimSizeCall` generator in SparseTensorConversion.cpp * Changes `genLvlSizeCall` to perform no logic, just generate the function call. * Adds `createOrFold{Dim,Lvl}Call` functions to handle the logic of replacing `gen{Dim,Lvl}SizeCall` with constants whenever possible. The `createOrFoldDimCall` function replaces the old `sizeFromPtrAtDim`. * Adds `{get,fill}DimSizes` functions for iterating `createOrFoldDimCall` across the whole type. These functions replace the old `sizesFromPtr`. * Adds `{get,fill}DimShape` functions for lowering a `ShapedType` into constants. These functions replace the old `sizesFromType`. * Changes the `DimOp` rewrite to do the right thing. * Changes the `ExpandOp` rewrite to compute the proper expansion size. Depends On D138365 Reviewed By: aartbik Differential Revision: https://reviews.llvm.org/D139165
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