The test attempts to use -1 as carry-in for v_addc_*.

Before writing r314522, I did actually test this on real hardware,
and found that it doesn't work. So r314522 is correct in restricting
the carry-in operand: just remove those tests to make things pass
again.

llvm-svn: 314530

'InlineAsmIdentifierInfo' is now a struct - notify Sema.h it isn't a class anymore

llvm-svn: 314529

llvm-svn: 314528

Summary:
Demanglers such as libiberty know how to strip suffixes of the form
\.[a-zA-Z]+\.\d+, but our current promoted value suffixes are
.llvm.${modulehash}, where the module hash is in hex. Change the
module hash to decimal to allow demanglers to handle this.

Reviewers: danielcdh

Subscribers: llvm-commits, inglorion

Differential Revision: https://reviews.llvm.org/D38405

llvm-svn: 314527

Suspected failure due to LSan's atexit and exit interception behavior.

Reviewers: kcc, kubamracek, bogner, hfinkel, alekseyshl, Hahnfeld, gtbercea

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37810

llvm-svn: 314526

These functions print a multi-line and sorted representation of unions
of polyhedra. Each polyhedron (basic_{ast/map}) has its own line.
First sort key is the polyhedron's hierachical space structure.
Secondary sort key is the lower bound of the polyhedron, which should
ensure that the polyhedral are printed in approximately ascending order.

Example output of dumpPw():
[p_0, p_1, p_2] -> {
  Stmt0[0] -> [0, 0];
  Stmt0[i0] -> [i0, 0] : 0 < i0 <= 5 - p_2;
  Stmt1[0] -> [0, 2] : p_1 = 1 and p_0 = -1;
  Stmt2[0] -> [0, 1] : p_1 >= 3 + p_0;
  Stmt3[0] -> [0, 3];
}

In contrast dumpExpanded() prints each point in the sets, unless there
is an unbounded dimension that cannot be expandend.
This is useful for reduced test cases where the loop counts are set to
some constant to understand a bug.

Example output of dumpExpanded(
{ [MemRef_A[i0] -> [i1]] : (exists (e0 = floor((1 + i1)/3): i0 = 1 and
3e0 <= i1 and 3e0 >= -1 + i1 and i1 >= 15 and i1 <= 25)) or (exists (e0
= floor((i1)/3): i0 = 0 and 3e0 < i1 and 3e0 >= -2 + i1 and i1 > 0 and
i1 <= 11)) }):

{
  [MemRef_A[0] ->[1]];
  [MemRef_A[0] ->[2]];
  [MemRef_A[0] ->[4]];
  [MemRef_A[0] ->[5]];
  [MemRef_A[0] ->[7]];
  [MemRef_A[0] ->[8]];
  [MemRef_A[0] ->[10]];
  [MemRef_A[0] ->[11]];
  [MemRef_A[1] ->[15]];
  [MemRef_A[1] ->[16]];
  [MemRef_A[1] ->[18]];
  [MemRef_A[1] ->[19]];
  [MemRef_A[1] ->[21]];
  [MemRef_A[1] ->[22]];
  [MemRef_A[1] ->[24]];
  [MemRef_A[1] ->[25]]
}

Differential Revision: https://reviews.llvm.org/D38349

llvm-svn: 314525

Fix Modules/{builtin-import.mm,umbrella-header-include-builtin.mm} to be able to handle non-Darwin targets

Summary: Also makes them pass on Darwin, if the default target triple is a Linux triple.

Reviewers: bruno, rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D38364

llvm-svn: 314524

This implement the insertion operator for DWARF address ranges so they
are consistently printed as [LowPC, HighPC).

While a dump method might have felt more consistent, it is used
exclusively for printing error messages in the verifier and never used
for actual dumping. Hence this approach is more intuitive and creates
less clutter at the call sites.

Differential revision: https://reviews.llvm.org/D38395

llvm-svn: 314523

The hardware will only forward EXEC_LO; the high 32 bits will be zero.

Additionally, inline constants do not work. At least,

   v_addc_u32_e64 v0, vcc, v0, v1, -1

which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.

The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine

   s_mov_b64 s[0:1], exec
   v_cndmask_b32_e64 v0, v1, v2, s[0:1]

into

   v_mov_b32 v0, v3

but it's not particularly high priority.

Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*

llvm-svn: 314522

llvm-svn: 314521

llvm-svn: 314520

Contributed-by: Nandini Singhal <cs15mtech01004@iith.ac.in>

Differential Revision: https://reviews.llvm.org/D38322

llvm-svn: 314519

llvm-svn: 314518

Summary:
Currently, getGEPCost() returns TCC_FREE whenever a GEP is a legal addressing mode in the target.
However, since it doesn't check its actual users, it will return FREE even in cases
where the GEP cannot be folded away as a part of actual addressing mode.
For example, if an user of the GEP is a call instruction taking the GEP as a parameter,
then the GEP may not be folded in isel.

Reviewers: hfinkel, efriedma, mcrosier, jingyue, haicheng

Reviewed By: hfinkel

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D38085

llvm-svn: 314517

Implement shouldCoalesce() to help regalloc avoid running out of GR128
registers.

If a COPY involving a subreg of a GR128 is coalesced, the live range of the
GR128 virtual register will be extended. If this happens where there are
enough phys-reg clobbers present, regalloc will run out of registers (if
there is not a single GR128 allocatable register available).

This patch tries to allow coalescing only when it can prove that this will be
safe by checking the (local) interval in question.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D37899
https://bugs.llvm.org/show_bug.cgi?id=34610

llvm-svn: 314516

llvm-svn: 314515

Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val)

Differential Revision: https://reviews.llvm.org/D38161

llvm-svn: 314514

result was never initialized to zero which sometimes failed the test.

llvm-svn: 314513

TEST_BIG_ENDIAN() performs compile tests that will fail with
-nodefaultlibs when building under LLVM_USE_SANITIZER.

Differential Revision: https://reviews.llvm.org/D38277

llvm-svn: 314512

New instructions are added to AArch32 and AArch64 to aid
floating-point multiplication and addition of complex numbers, where
the complex numbers are packed in a vector register as a pair of
elements. The Imaginary part of the number is placed in the more
significant element, and the Real part of the number is placed in the
less significant element.

This patch adds assembler for the ARM target.

Differential Revision: https://reviews.llvm.org/D36789

llvm-svn: 314511

Change-Id: I360abccee12cae29bd2ac4f8399c9ecc92eb7f13
llvm-svn: 314510

This commit adds a refactoring engine design document that talks about the
design and provides several example of how the engine can be used.

Differential Revision: https://reviews.llvm.org/D37976

llvm-svn: 314509

InlineAsmIdentifierInfo was declared a class in some places and a class in others.

llvm-svn: 314508

Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.

Recommitting r314497. This version does not contain test which fails
when compiler is not build in debug mode.

Differential Revision: https://reviews.llvm.org/D37328

llvm-svn: 314507

Added test relies on the compiler being built in debug mode,
which may not be the case.

This reverts commit r314497.

llvm-svn: 314506

Add missing license information to MicroMipsInstrFPU.td and
fix most of the formatting errors present. Others will be
addressed in a follow up commits.

llvm-svn: 314505

Added additional tests for vector multiplications with multipliers that are:
 * powers of 2 displaced by 1,
 * product of a power of 2 displaced by one with another power of 2.

Patch by @pacxx (Michael Haidl)

Differential Revision: https://reviews.llvm.org/D38350

llvm-svn: 314504

Add missing test cases for dext, dextm, dextu, dins, dinsm and
dinsu instructions.

Differential Revision: https://reviews.llvm.org/D37741

llvm-svn: 314503

Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new ones.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D37752

llvm-svn: 314502

Summary:
Added support for scratch (including spilling) for OS type amdpal:
generates code to set up the scratch descriptor if it is needed.

With amdpal, the scratch resource descriptor is loaded from offset 0 of
the global information table. The low 32 bits of the address of the
global information table is passed in s0.

Added amdgpu-git-ptr-high function attribute to hard-wire the high 32
bits of the address of the global information table. If the function
attribute is not specified, or is 0xffffffff, then the backend generates
code to use the high 32 bits of pc.

The documentation for the AMDPAL ABI will be added in a later commit.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye

Differential Revision: https://reviews.llvm.org/D37483

llvm-svn: 314501

Summary:
This operating system type represents the AMDGPU PAL runtime, and will
be required by the AMDGPU backend in order to generate correct code for
this runtime.

Currently it generates the same code as not specifying an OS at all.
That will change in future commits.

Patch from Tim Corringham.

Subscribers: arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D37380

llvm-svn: 314500

Patch by S. Gilles!

Differential Revision: https://reviews.llvm.org/D28148

llvm-svn: 314499

This patch introduces 3 helper functions: error(), warn() and note() to
make printing  during verification more consistent. When supported, the
respective prefixes are printed in color using the same color scheme as
clang.

Differential revision: https://reviews.llvm.org/D38368

llvm-svn: 314498

Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.

Differential Revision: https://reviews.llvm.org/D37328

llvm-svn: 314497

llvm-svn: 314496

Convert all common symbols to regular symbols after scan.
This means that the downstream code does not to handle common symbols as a special case.

Differential Revision: https://reviews.llvm.org/D38137

llvm-svn: 314495

Allow the proper recognition of Enum values and global variables inside ms inline-asm memory / immediate expressions, as they require some additional overhead and treated incorrect if doesn't early recognized.
supersedes D33278, D35774

Differential Revision: https://reviews.llvm.org/D37413

llvm-svn: 314494

Allow the proper recognition of Enum values and global variables inside ms inline-asm memory / immediate expressions, as they require some additional overhead and treated incorrect if doesn't early recognized.
supersedes D33278, D35774

Differential Revision: https://reviews.llvm.org/D37412

llvm-svn: 314493

This extends SVN r314197 from the arm parts to the whole file.

Differential Revision: https://reviews.llvm.org/D38381

llvm-svn: 314492

This is slightly less verbose for the common case of a single build directory
and more intuitive when using this API directly from the interpreter.

llvm-svn: 314491