llvm-svn: 316516

llvm-svn: 316515

llvm-svn: 316514

llvm-svn: 316513

llvm-svn: 316512

llvm-svn: 316511

llvm-svn: 316510

llvm-svn: 316509

llvm-svn: 316508

WebassemblyAsmPrinter.h: Include WebAssemblyMachineFunctionInfo for use with MachineFunction::getInfo

llvm-svn: 316507

llvm-svn: 316506

llvm-svn: 316505

llvm-svn: 316504

[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

llvm-svn: 316503

link.exe supports this option to convert warnings into errors, and it's
useful to support in LLD as well.

Differential Revision: https://reviews.llvm.org/D39148

llvm-svn: 316502

LLD's handling of boolean flags is suboptimal:
* All boolean flags have a corresponding `:no` flag to turn the flag
  off, and the linker should scan for both the non-suffixed and suffixed
  flags (and the last one should win), but right now it only scans for
  either the suffixed or non-suffixed flag (depending on the default
  flag value).
* The `B` multiclass only allows specifying help text for the suffixed
  (`:no`) flag, but for some flags (e.g. `/appcontainer`) the help text
  should be associated with the non-suffixed flag instead.

Extend the `B` multiclass to have help text for both non-suffixed and
suffixed flag variants, and alter the existing help text accordingly in
some cases. Scan for both the non-suffixed and suffixed variants in the
driver and set config values accordingly.

This should mostly have no behavior change, apart from the added help
text and the modified argument scanning. Some flags are handled slightly
differently now, however; for example, LLD would previously always treat
64-bit images as large address aware, whereas `/largeaddressaware:no` is
now respected for 64-bit images (which is also how link.exe behaves).

Differential Revision: https://reviews.llvm.org/D39216

llvm-svn: 316501

rL316268 / D39122 has fixed PR35009, and now when in C,
these three(?) diagnostics properly use the enum's underlying
datatype.

While it was fixed, the test coverage was clearly insufficient,
because the -Wsign-compare change didn't show up in any of the
tests, until it was reported in the post-commit mail for rL316268.

So add the test for the -Wsign-compare diagnostic for enum
for C code, and while there, document this in the release notes.

The fix itself was obviously correct, so unless we want to silence
this new diagnosed case, i deem this commit to be NFC.

llvm-svn: 316500

I just didn't know that ArgList had that function.

llvm-svn: 316499

llvm-svn: 316498

This reverts commit r316417, which causes internal compiles to OOM.
I don't unfortunately have a self-contained test case but will follow up
with courbet.

llvm-svn: 316497

llvm-svn: 316496

If particular target supports volatile memory access operations, we can
avoid AS casting to generic AS. Currently it's only enabled in NVPTX for
loads and stores that access global & shared AS.

Differential Revision: https://reviews.llvm.org/D39026

llvm-svn: 316495

llvm-svn: 316494

Subscribers: mgorny, aheejin

Differential Revision: https://reviews.llvm.org/D39250

llvm-svn: 316493

Adding the scheduling information for the Browadwell (BDW) CPU target.

This patch adds the instruction scheduling information for the Broadwell (BDW) architecture target by adding the file X86SchedBroadwell.td located under the X86 Target.
We used the scheduling information retrieved from the Broadwell architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each BDW instruction.

The patch continues the scheduling replacement and insertion effort started with the SandyBridge (SNB) target in r310792, the Haswell (HSW) target in r311879, the SkylakeClient (SKL) target in rL313613 + rL315978 and the SkylakeServer (SKX) in rL315175.

Performance fluctuations may be expected due to code alignment effects.

Reviewers: zvi, RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D39054

Change-Id: If6f799e5ff60e1091c8d43b05ea78c53581bae01
llvm-svn: 316492

llvm-svn: 316491

We need to use a stable sort on instantiation and expansion sub-views to
produce consistent output. Fortunately, we've gotten lucky and the tests
have checks for the stable order.

This is needed to unblock D39245. Once that lands, we'll have better
test coverage for sort non-determinism.

llvm-svn: 316490

llvm-svn: 316489

Fixed passing of VLAs and variably-modified types to outlined functions.
Synchronized passing with the types codegen.

llvm-svn: 316488

Summary:
Similar to NetBSD, in FreeBSD, the first returned entry when callbacks
are done via dl_iterate_phdr will return the main program.  Ignore that
entry when checking that the dynamic ASan lib is loaded first.

Reviewers: eugenis, krytarowski, emaste, joerg

Reviewed By: eugenis, krytarowski

Subscribers: kubamracek, llvm-commits

Differential Revision: https://reviews.llvm.org/D39253

llvm-svn: 316487

llvm-svn: 316486

llvm-svn: 316485

Builder save/restores insertion pointer when emitting addr space cast
for alloca, but does not save/restore debug loc, which causes verifier
failure for certain call instructions.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D39069

llvm-svn: 316484

Differential Revision: https://reviews.llvm.org/D39140

llvm-svn: 316483

Fixes atoi and strtol interception.

llvm-svn: 316482

Previous implementation for per-function scope
is incorrect and too conservative.

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 316481

I missed a dereference of `Matched` that preceeded the new check. Thanks to
Justin Bogner for spotting it.

llvm-svn: 316480

This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,

  %1(s64) = COPY %0(s64)

would now be written as

  %1:gpr(s64) = COPY %0(s64)

While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.

Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.

llvm-svn: 316479

If we have the situation where a Swap feeds a Splat we can sometimes change the
  index on the Splat and then remove the Swap instruction.

Fixed the test case that was failing and recommit after pulling the original
  commit.

  Original revision is here: https://reviews.llvm.org/D39009

llvm-svn: 316478

This creates ODR violations if the function is called from another inline                                                                   function in a header and also creates binary bloat from duplicate definitions.

llvm-svn: 316477