This is the main patch that introduced the new EFLAGS lowering infrastructure.
All the source merges were clean, but the tests required help to merge.
Specifically, I had to regenerate the CHECK lines in the tests (using the trunk
update_llc_test_checks.py script) because trunk has copy propagation that the
branch doesn't. I also had to update the MIR test to use the old MIR syntax for
physical registers (%name instead of $name).

llvm-svn: 332933

instructions.

This is necessary to fully merge the EFLAGS fix patch series.

llvm-svn: 332932

subsequent cherrypicks to be much cleaner.

llvm-svn: 332928

These required skipping the updates to the update test scripts. Note that to
regenerate these tests you'll need to use the test update script close to trunk
rather than on the branch. =/

llvm-svn: 332902

The CHECK lines in the trunk version don't work due to unrelated (unmerged)
changes to the backend.

llvm-svn: 332900

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r330037 | sdardis | 2018-04-13 09:09:07 -0700 (Fri, 13 Apr 2018) | 21 lines

[mips] Materialize constants for multiplication

Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.

The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.

For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant

This resolves PR36884.

Thanks to npl for reporting the issue!

Reviewers: abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D45316

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llvm-svn: 332782

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r329268 | sdardis | 2018-04-05 03:30:17 -0700 (Thu, 05 Apr 2018) | 2 lines

[mips] Regenerate test before posting patch for constant multiplication (NFC)

------------------------------------------------------------------------

llvm-svn: 332778

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r324885 | atanasyan | 2018-02-12 04:21:55 -0800 (Mon, 12 Feb 2018) | 8 lines

[mips] Fix 'l' constraint handling for types smaller than 32 bits

In case of correct using of the 'l' constraint llvm now generates valid
code; otherwise it shows an error message. Initially these triggers an
assertion.

This commit is the same as r324869 with fixed the test's file name.

------------------------------------------------------------------------

llvm-svn: 332776

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r322266 | smaksimovic | 2018-01-11 02:07:47 -0800 (Thu, 11 Jan 2018) | 7 lines

[Mips] Handle one byte unsupported relocations

Fail gracefully instead of crashing upon encountering
this type of relocation.

Differential revision: https://reviews.llvm.org/D41857

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llvm-svn: 332765

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r331990 | whitequark | 2018-05-10 08:05:47 -0700 (Thu, 10 May 2018) | 15 lines

[PR37339] Fix assertion in FunctionComparator::cmpInlineAsm

Fixes bug https://bugs.llvm.org/show_bug.cgi?id=37339.

InlineAsm is only uniqued if the FunctionTypes are exactly the
same, while cmpTypes() for example considers all pointer types
in the default address space to be the same. For this reason
the end of cmpInlineAsm() can be reached.

This patch replaces the unreachable assertion with a check that
the function types are not identical.

Differential Revision: https://reviews.llvm.org/D46495

Reviewers: jfb
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llvm-svn: 332678

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r332342 | whitequark | 2018-05-15 04:31:07 -0700 (Tue, 15 May 2018) | 23 lines

[MergeFunctions] Fix merging of small weak functions

When two interposable functions are merged, we cannot replace
uses and have to emit calls to a common internal function. However,
writeThunk() will not actually emit a thunk if the function is too
small. This leaves us in a broken state where mergeTwoFunctions
already rewired the functions, but writeThunk doesn't do anything.

This patch changes the implementation so that:

 * writeThunk() does just that.
 * The direct replacement of calls is moved into mergeTwoFunctions()
   into the non-interposable case only.
 * isThunkProfitable() is extracted and will be called for
   the non-iterposable case always, and in the interposable case
   only if uses are still left after replacement.

This issue has been introduced in https://reviews.llvm.org/D34806,
where the code for checking thunk profitability has been moved.

Differential Revision: https://reviews.llvm.org/D46804

Reviewed By: whitequark
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llvm-svn: 332662

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r324581 | sjoerdmeijer | 2018-02-08 00:39:05 -0800 (Thu, 08 Feb 2018) | 12 lines

[AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported

We were generating "fmov h0, wzr" instructions when FullFP16 is not enabled.
I've not added any tests, because the problem was visible in:
test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll,
which I had to change: I don't think Cyclone has FullFP16 enabled
by default, so it shouldn't be using this v8.2a instruction.

I've also removed these rdar tags, please shout if there are any objections.

Differential Revision: https://reviews.llvm.org/D43020

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llvm-svn: 332655

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r323816 | evandro | 2018-01-30 13:14:11 -0800 (Tue, 30 Jan 2018) | 5 lines

[AArch64] Expand testing of zero cycle zeroing

Make sure that r321824 doesn't change zeroing.

Differential revision: https://reviews.llvm.org/D42089
------------------------------------------------------------------------

llvm-svn: 332651

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r330927 | sepavloff | 2018-04-26 01:08:25 -0700 (Thu, 26 Apr 2018) | 2 lines

Make test more platform neutral

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llvm-svn: 332650

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r330926 | sepavloff | 2018-04-25 23:28:47 -0700 (Wed, 25 Apr 2018) | 9 lines

[ConfigFiles] Update argument strings when merging argrument lists

Implementation of `InputArgList` assumes its field `ArgStrings` contains
strings for each argument exactly in the same order. This condition was
broken when arguments from config file and from invocation were merged.

This change fixes https://bugs.llvm.org/show_bug.cgi?id=37196 (Clang
config files can crash argument handling).

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llvm-svn: 332649

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r332444 | psmith | 2018-05-16 02:33:25 -0700 (Wed, 16 May 2018) | 20 lines

[AArch64] Support "S" inline assembler constraint

This patch re-introduces the "S" inline assembler constraint. This matches
an absolute symbolic address or a label reference. The primary use case is

asm("adrp %0, %1\n\t"
    "add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var));

I say re-introduces as it seems like "S" was implemented in the original
AArch64 backend, but it looks like it wasn't carried forward to the merged
backend. The original implementation had A and L modifiers that could be
used to print ":lo12:" to the string. It looks like gcc doesn't use these
and :lo12: is expected to be written in the inline assembly string so I've
not implemented A and L. Clang already supports the S modifier.

Fixes PR37180

Differential Revision: https://reviews.llvm.org/D46745

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llvm-svn: 332644

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r323053 | dhinton | 2018-01-20 16:29:00 -0800 (Sat, 20 Jan 2018) | 9 lines

[cmake] Don't build Native llvm-config when cross compiling if passed by user.

Summary:
Rename LLVM_CONFIG_EXE to LLVM_CONFIG_PATH, and avoid building it if
passed in by user.  This is the same way CLANG_TABLEGEN and
LLVM_TABLEGEN are handled, e.g., when -DLLVM_OPTIMIZED_TABLEGEN=ON is
passed.

Differential Revision: https://reviews.llvm.org/D41806
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llvm-svn: 332568

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r327354 | dyung | 2018-03-12 17:41:44 -0700 (Mon, 12 Mar 2018) | 2 lines

Add missing "env" so that test added in r327322 passes on Windows bots.

------------------------------------------------------------------------

llvm-svn: 332566

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r329414 | ctopper | 2018-04-06 09:16:43 -0700 (Fri, 06 Apr 2018) | 3 lines

[X86] Merge itineraries for CLC, CMC, and STC.

These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation.
------------------------------------------------------------------------

llvm-svn: 332565

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r328944 | chandlerc | 2018-04-01 14:47:55 -0700 (Sun, 01 Apr 2018) | 4 lines

[x86] Expose more of the condition conversion routines in the public API
for X86's instruction information. I've now got a second patch under
review that needs these same APIs. This bit is nicely orthogonal and
obvious, so landing it. NFC.
------------------------------------------------------------------------

llvm-svn: 332564

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r325446 | dim | 2018-02-17 13:04:35 -0800 (Sat, 17 Feb 2018) | 28 lines

[X86] Add 'sahf' CPU feature to frontend

Summary:
Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the
`+sahf` feature for the backend, for bug 36028 (Incorrect use of
pushf/popf enables/disables interrupts on amd64 kernels).  This was
originally submitted in bug 36037 by Jonathan Looney
<jonlooney@gmail.com>.

As described there, GCC also uses `-msahf` for this feature, and the
backend already recognizes the `+sahf` feature. All that is needed is to
teach clang to pass this on to the backend.

The mapping of feature support onto CPUs may not be complete; rather, it
was chosen to match LLVM's idea of which CPUs support this feature (see
lib/Target/X86/X86.td).

I also updated the affected test case (CodeGen/attr-target-x86.c) to
match the emitted output.

Reviewers: craig.topper, coby, efriedma, rsmith

Reviewed By: craig.topper

Subscribers: emaste, cfe-commits

Differential Revision: https://reviews.llvm.org/D43394

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llvm-svn: 332560

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r328408 | echristo | 2018-03-23 19:56:58 -0700 (Fri, 23 Mar 2018) | 1 line

Add REQUIRES lines for the targets being checked in this test.
------------------------------------------------------------------------

llvm-svn: 332552

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r332197 | dim | 2018-05-13 07:32:23 -0700 (Sun, 13 May 2018) | 4 lines

Follow-up to rL332176 by adding a test case for PR37264.

Noticed by Simon Pilgrim.

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llvm-svn: 332264

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r332176 | dim | 2018-05-12 12:59:54 -0700 (Sat, 12 May 2018) | 20 lines

Clear converters map after X86 Domain Reassignment to avoid crashes

Summary:
As reported in PR37264, in some cases the X86 Domain Reassignment
`runOnMachineFunction()` is called twice.  Because it only deletes the
`.second` members of its `InstrConverterBaseMap`, and does not clean up
the map itself, this can lead to double frees and crashes.

Use `DeleteContainerSeconds()` instead, so the `Converters` map can
safely be reinitialized and its members re-deleted for each X86 Domain
Reassignment pass.

Reviewers: guyblank, craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46425

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llvm-svn: 332263

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r332103 | gberry | 2018-05-11 09:25:06 -0700 (Fri, 11 May 2018) | 24 lines

[AArch64] Fix performPostLD1Combine to check for constant lane index.

Summary:
performPostLD1Combine in AArch64ISelLowering looks for vector
insert_vector_elt of a loaded value which it can optimize into a single
LD1LANE instruction.  The code checking for the pattern was not checking
if the lane index was a constant which could cause two problems:

- an assert when lowering the LD1LANE ISD node since it assumes an
  constant operand

- an assert in isel if the lane index value depends on the
  post-incremented base register

Both of these issues are avoided by simply checking that the lane index
is a constant.

Fixes bug 35822.

Reviewers: t.p.northover, javed.absar

Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D46591
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llvm-svn: 332158

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r327322 | arphaman | 2018-03-12 12:36:29 -0700 (Mon, 12 Mar 2018) | 7 lines

[Tooling] Clear the PreambleSrcLocCache when preamble is discarded during reparsing

This ensures that diagnostics are not remapped to incorrect preamble locations after
the second reparse with a remapped header file occurs.

rdar://37502480

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llvm-svn: 332113

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r327562 | mstorsjo | 2018-03-14 22:17:24 +0200 (Wed, 14 Mar 2018) | 1 line

[MinGW] Add support for the GNU ld flag --kill-at
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llvm-svn: 332084

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r327561 | mstorsjo | 2018-03-14 22:17:16 +0200 (Wed, 14 Mar 2018) | 16 lines

[COFF] Add support for the GNU ld flag --kill-at

GNU ld has got a number of different flags for adjusting how to
behave around stdcall functions. The --kill-at flag strips the
trailing sdcall suffix from exported functions (which otherwise
is included by default in MinGW setups).

This also strips it from the corresponding import library though.
That makes it hard to link to such an import library from code
that calls the functions - but this matches what GNU ld does with
this flag. Therefore, this flag is probably not sensibly used
together with import libraries, but probably mostly when creating
some sort of plugin, or if creating the import library separately
with dlltool.

Differential Revision: https://reviews.llvm.org/D44292
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r327567 | mstorsjo | 2018-03-14 22:31:31 +0200 (Wed, 14 Mar 2018) | 4 lines

[test] Fix a temp filename in a test from SVN r327561. NFC.

An earlier file name accidentally slipped through into the committed
version.
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llvm-svn: 332083

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r330792 | gberry | 2018-04-24 19:17:56 -0700 (Tue, 24 Apr 2018) | 14 lines

[DivRemPairs] Fix non-determinism in use list order.

Summary:
Use a MapVector instead of a DenseMap for RemMap since it is iteratated
over and the order of iteration can effect the order that new
instructions are created.  This can in turn effect the use list order of
div/rem input values if multiple new instructions are created that share
any input values.

Reviewers: spatel

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D45858
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llvm-svn: 332080

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r326172 | mstorsjo | 2018-02-26 22:26:35 -0800 (Mon, 26 Feb 2018) | 7 lines

[MinGW] Ignore the --start-group --end-group parameters

These are required for handling circular dependencies between
static libraries, which is something that lld-link always does without
any extra parameters.

Differential Revision: https://reviews.llvm.org/D43786
------------------------------------------------------------------------

llvm-svn: 332044

This reverts commit r332001.

I forgot to run make check before committing and the tests cases with
this patch fail.

llvm-svn: 332008

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r328039 | mstorsjo | 2018-03-20 13:37:51 -0700 (Tue, 20 Mar 2018) | 8 lines

[X86] Don't use the MSVC stack protector names on mingw

Mingw uses the same stack protector functions as GCC provides
on other platforms as well.

Patch by Valentin Churavy!

Differential Revision: https://reviews.llvm.org/D27296
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llvm-svn: 332001

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r327540 | ctopper | 2018-03-14 10:57:19 -0700 (Wed, 14 Mar 2018) | 7 lines

[X86] Add back fast-isel code for handling i8 shifts.

I removed this in r316797 because the coverage report showed no coverage and I thought it should have been handled by the auto generated table. I now see that there is code that bypasses the table if the shift amount is out of bounds.

This adds back the code. We'll codegen out of bounds i8 shifts to effectively (amount & 0x1f). The 0x1f is a strange quirk of x86 that shift amounts are always masked to 5-bits(except 64-bits). So if the masked value is still out bounds the result will be 0.

Fixes PR36731.
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llvm-svn: 331815

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r330189 | whitequark | 2018-04-17 07:52:43 -0700 (Tue, 17 Apr 2018) | 7 lines

[LLVM-C] [PR34633] Avoid calling ->dump() methods from LLVMDump*.

LLVMDump* functions are available in Release builds too.

Patch by Brenton Bostick.

Differential Revision: https://reviews.llvm.org/D44600
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llvm-svn: 331804

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r326429 | d0k | 2018-03-01 03:31:44 -0800 (Thu, 01 Mar 2018) | 1 line

[SCCP] Fix unused variable warning in release builds.
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llvm-svn: 331722

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r330186 | nemanjai | 2018-04-17 06:07:01 -0700 (Tue, 17 Apr 2018) | 11 lines

[PowerPC] Mark the BDNZ intrinsic as NoDuplicate

Duplicating this intrinsic is not generally valid because it has the side-effect
of decrementing the CTR. Any passes that duplicate it would need to be taught to
keep the regions formed completely disjoint.
This patch should be NFC for typical uses as CTRLoops runs after the remaining
loop passes. It only affects situations where the loop passes are scheduled on
the IR after the codegen passes (as is the case with some JIT pipelines).

Fixes https://bugs.llvm.org/show_bug.cgi?id=37050

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llvm-svn: 331716

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r329335 | lhames | 2018-04-05 12:37:05 -0700 (Thu, 05 Apr 2018) | 15 lines

[RuntimeDyld][PowerPC] Use global entry points for calls between sections.

Functions in different objects may use different TOCs, so calls between such
functions should use the global entry point of the callee which updates the
TOC pointer.

This should fix a bug that the Numba developers encountered (see
https://github.com/numba/numba/issues/2451).

Patch by Olexa Bilaniuk. Thanks Olexa!

No RuntimeDyld checker test case yet as I am not familiar enough with how
RuntimeDyldELF fixes up call-sites, but I do not want to hold up landing
this. I will continue to work on it and see if I can rope some powerpc
experts in.
------------------------------------------------------------------------

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r329355 | lhames | 2018-04-05 14:56:55 -0700 (Thu, 05 Apr 2018) | 4 lines

[RuntimeDyld][PowerPC] Add a test case for r329335.

Checks that calls to different sections go to the function's global entry point,
rather than the local one.
------------------------------------------------------------------------

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r329573 | krasimir | 2018-04-09 07:29:23 -0700 (Mon, 09 Apr 2018) | 11 lines

[RuntimeDyld][PowerPC] Fix a newly added test in r329355

Summary: The bit widths are wrong.

Reviewers: bkramer, lhames, hans

Reviewed By: hans

Subscribers: hans, nemanjai, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D45361
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llvm-svn: 331715

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r328400 | echristo | 2018-03-23 17:07:38 -0700 (Fri, 23 Mar 2018) | 6 lines

Allow FDE references outside the +/-2GB range supported by PC relative
offsets for code models other than small/medium. For JIT application,
memory layout is less controlled and can result in truncations
otherwise.

Patch based on one by Olexa Bilaniuk!
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llvm-svn: 331714

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r329761 | gberry | 2018-04-10 14:43:03 -0700 (Tue, 10 Apr 2018) | 13 lines

[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.

Summary:
When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.

Reviewers: mcrosier

Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45502
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llvm-svn: 330209

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r322373 | d0k | 2018-01-12 07:03:24 -0800 (Fri, 12 Jan 2018) | 4 lines

[PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate

I'm not even sure if this transform is ever worth it, but this at least
stops the bleeding.
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llvm-svn: 330082