A move towards using the generic ISD::ABDU nodes on more backends

Also support ISD::ABDS for v4i32 types using the existing signbit flip trick

PowerPC has a select(icmp_ugt(x,y),sub(x,y),sub(y,x)) -> abdu(x,y) combine that I intend to move to DAGCombiner in a future patch.

The ABS(SUB(X,Y)) -> PPCISD::VABSD(X,Y,1) v4i32 combine wasn't legal (https://alive2.llvm.org/ce/z/jc2hLU) - so I've removed it, having already added the legal sub nsw tests equivalent.

Differential Revision: https://reviews.llvm.org/D142313

To do this we need to remove the always matching behavior from condop.
This requires us to add more 'select' isel patterns with a bare GPR
as the condition.

Rename condop/invcondop to riscv_setne/riscv_seteq.

This centralizes the ADDI/XORI/XOR tricks into one place.

As detailed on D142313, this fold should be restricted by sub nsw

Ignoring std::array type when matching 'std:array == std::array()'.
In such case we shouldn't propose to use empty().

Fixes: https://github.com/llvm/llvm-project/issues/48286

Differential Revision: https://reviews.llvm.org/D144217

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.

`views::as_rvalue` was implemented in D137637, but we forgot to set the feature test macro.
Fixes #60986.

Reviewed By: Mordante, #libc

Spies: libcxx-commits, arichardson

Differential Revision: https://reviews.llvm.org/D144781

The two tests were failing on arm64-linux with:
BOLT-ERROR: invalid target 'x86-64'.

Differential Revision: https://reviews.llvm.org/D144593

This paper is about changes to the assert macro, but assert.h is not
provided by the compiler, so there's no work for Clang to do to support
this feature.

Reviewed By: Mordante, JMazurkiewicz, #libc

Differential Revision: https://reviews.llvm.org/D144629

This implements WG14 N2934
(https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2934.pdf), which
adds keywords for alignas, alignof, bool, static_assert, and
thread_local in C, as aliases for _Alignas, _Alignof, _Bool,
_Static_assert, and _Thread_local. We already supported the keywords in
C2x mode, but this completes support by adding pre-C2x compat warnings
and updates the stdalign.h header in freestanding mode.

Previous the stack slot for spilling base pointer register is allocated
after the stack realignment. When the stack is naturally aligned the
stack slot is share with other data that allocated from stack and cause
data corrupt. Another issue is the stack slot for save/restore the
callee saved register is not fixed for each function. It depends on the
register usage of them in each function.

This patch is to recalculate the offset the stack slot for base pointer
register during the prolog/epilog insert pass, and allocate the stack
slot when spilling callee saved registers.

Differential Revision: https://reviews.llvm.org/D144625

The result value of `getelementptr inbounds (TY, null, not zero)` is a poison value. We can think of it as undefined behavior.

> Please let me know if there is anything I don't understand correctly.

Reviewed By: nikic, xbolva00

Differential Revision: https://reviews.llvm.org/D144563

For tests in the OpenMP sub-directory the `omp` prefix is removed.

For tests in the OpenMP sub-directory the `omp` prefix is removed.

Now that the test files are in the OpenMP subdirectory, remove the
`omp` prefix.

Previously, given a pointer-to-member type such as `Foo const Bar::*`,
clang-format would see the `const Bar::` part as a regular type name
with scope resolution operators, and with `QualifierAlignment: Right` it
would attempt to "fix" it, resulting in `Foo Bar::const *`, a syntax
error.

This patch no longer allows qualifiers to be moved across `::*`.

Fixes https://github.com/llvm/llvm-project/issues/60898

Reviewed By: owenpan, MyDeveloperDay, HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D144537

The previous version set the indentation directly using IndentForLevel,
however, this has a few caveats, namely:

* IndentForLevel applies to all scopes of the entire program being
  formatted, but this indentation should only be adjusted for scopes
  of namespaces.

* The method it used only set the correct indent amount if one wasn't
  already set for a given level, meaning it didn't work correctly if
  anything with indentation preceded a namespace keyword. This
  includes preprocessing directives if using IndentPPDirectives.

This patch instead reduces the Level of all lines within namespaces
which are compacted by CompactNamespaces. This means they will get
correct indentation using the normal process.

Fixes https://github.com/llvm/llvm-project/issues/60843

Reviewed By: owenpan, MyDeveloperDay, HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D144296

This reverts commit f07bb001.

Failed to squash this commit

Revert "[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size."

This reverts commit 7910ed1d.

Accidentally failed to squash a commit

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.

We had identical patterns for TH_FLRW, TH_FSRW, TH_FLRD, and TH_FSRD
under both IsRV32 and IsRV64.

[lld][RISCV] Avoid error when encountering unrecognised ISA extensions/versions in RISC-V attributes

This patch follows on from this RFC thread
<https://discourse.llvm.org/t/rfc-resolving-issues-related-to-extension-versioning-in-risc-v/68472/>
and the ensuing discussion in the RISC-V LLVM sync-up call. The
consensus agreed that the behaviour change in LLD introduced in D138550
that results in object files including arch attributes with unrecognised
extensions or versions of extensions is a regression and should be
treated as such. As it stands, this logic means that LLD will error out
if trying to link a RISC-V object file from LLVM HEAD (rv32i2p0/rv64i2p0)
with one from current GCC (rv32i2p1/rv64i2p1 by default).

There's a bigger discussion about exactly when to warn vs error and so
on, and how to control that, and this patch doesn't attempt to address
all those questions. It simply tries to fix the problem with a minimally
invasive change, intended to be cherry-picked for 16.0.x (ideally
16.0.0, but queued for 16.0.1 if we're too late in the release cycle).

As you can see from the test changes, although the changed logic is
mostly more permissive, it will reject some embedded arch strings that
were accepted before. Because the same logic was previously used for
parsing human-written -march as for the arch attribute (intended to be
stored in normalised form), various short-hand formats were previously
accepted. Maintaining support for such ill-formed attributes would
substantially complicate the logic, and given the previous
implementation was so much stricter in every other way, was surely a bug
rather than a design choice.

Surprisingly, the precise rules for how numbers can be embedded into
extension names isn't fully defined (there is a PR to the ISA manual
that is not yet merged
<https://github.com/riscv/riscv-isa-manual/pull/718>).
In the absence of specific criteria for rejecting extensions names that
would be ambiguous in abbreviated form,
`RISCVISAInfo::parseArchStringNormalized` just pulls out the version
information from the end of each extension description.

Differential Revision: https://reviews.llvm.org/D144353

... for implicitly-generated copy constructors and copy assignment operators.

Differential Revision: https://reviews.llvm.org/D144694

I didn't understand why the other builtins have promotion logic,
or how it would apply for a ternary operation. Implicit conversions
are evil to begin with,  and even more so when the purpose is to get
an exact IR intrinsic. This checks all the arguments have the same type.

Add info about the "testing only" aspect of `--allow-unregistered-dialect` in the cl::opt desc (NFC)

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D144615

D135617 leftovers

Reviewed By: browneee, cryptoad

Differential Revision: https://reviews.llvm.org/D136308

ATOMIC_VAR_INIT has a trivial definition
`#define ATOMIC_VAR_INIT(value) (value)`,
is deprecated in C17/C++20, and will be removed in newer standards in
newer GCC/Clang (e.g. https://reviews.llvm.org/D144196).

ATOMIC_VAR_INIT has a trivial definition `#define ATOMIC_VAR_INIT(value) (value)`,
is deprecated in C17/C++20, and will be removed in newer standards.

Almost all printf conversions ending in '%' are undefined, but they're
traditionally treated as if the complete conversion specifier is "%%".
This patch modifies the parser to more closely match that behavior.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D144679

Add transform for `(and/or (icmp eq/ne A,-1),(icmp eq/ne A,-1+C))`->`(and/or (icmp eq/ne (and ~A,-1+C),0))`

This works of `-1+C` is a negative power of 2.

This can be more useful than the `AddAnd` case as `~A` does not
necessarily require materializing a constant. This makes the transform
worth it for X86 vector types.

Alive2 Links:
EQ: https://alive2.llvm.org/ce/z/P6u8cq
NE: https://alive2.llvm.org/ce/z/_Kkqp1

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D144284

Make `(and/or (icmp eq/ne A,C0), (icmp eq/ne A,C1))` where `IsPow(dif(C0,C1))` work for more patterns.

`(and/or (icmp eq/ne A,C0), (icmp eq/ne A,C1))` can be lowered to
`(icmp eq/ne (and (sub A, (smin C0, C1)), (not (sub (smax C0, C1), (smin C0, C1)))), 0)`
generically if `(sub (smax C0, C1), (smin C0,C1))` is a power of 2.

This covers the existing case of `(and/or (icmp eq/ne A, C_Pow2),(icmp eq/ne A, -C_Pow2))`
as well as other cases.

Alive2 Links:
EQ: https://alive2.llvm.org/ce/z/mLJiUW
NE: https://alive2.llvm.org/ce/z/TKnzUr

Differential Revision: https://reviews.llvm.org/D144283

Differential Revision: https://reviews.llvm.org/D144282

X ^ Pow2 is guranteed to flip one bit. We can use this to speedup
max/min by just selecting X with/without (or/andnot) the flipped bit
respectively.

Alive2 Links:
smax-neg: https://alive2.llvm.org/ce/z/j3QYFs
smin-neg: https://alive2.llvm.org/ce/z/bFYnQW
smax-pos: https://alive2.llvm.org/ce/z/4xYSxR
smin-pos: https://alive2.llvm.org/ce/z/H3RPKj
umax    : https://alive2.llvm.org/ce/z/P4oRcX
umin    : https://alive2.llvm.org/ce/z/vWZG6p

Differential Revision: https://reviews.llvm.org/D144606

Differential Revision: https://reviews.llvm.org/D144605