llvm-svn: 191774

llvm-svn: 191773

Summary: Pure refactoring, should be no semantic changes.

Reviewers: djasper

Reviewed By: djasper

CC: cfe-commits, klimek

Differential Revision: http://llvm-reviews.chandlerc.com/D1796

llvm-svn: 191772

llvm-svn: 191771

This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.

llvm-svn: 191770

This attribute allows users to use a modified C or C++ function as an ARM
exception-handling function and, with care, to successfully return control to
user-space after the issue has been dealt with.

rdar://problem/14207019

llvm-svn: 191769

It's a useful function to have around for target-specific attributes.

llvm-svn: 191768

As the comment says, we always want to use STOC for 32-bit stores.

llvm-svn: 191767

This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

llvm-svn: 191766

llvm-svn: 191765

Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers.  This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.

llvm-svn: 191764

- New ProcessInfo class to encapsulate information about child processes.
- Generalized the Wait() to support non-blocking wait on child processes.
- ExecuteNoWait() now returns a ProcessInfo object with information about
  the launched child. Users will be able to use this object to
  perform non-blocking wait.
- ExecuteNoWait() now accepts an ExecutionFailed param that tells if execution
  failed or not.

These changes will allow users to implement basic process parallel
tools.

Differential Revision: http://llvm-reviews.chandlerc.com/D1728

llvm-svn: 191763

llvm-svn: 191762

llvm-svn: 191760

llvm-svn: 191759

llvm-svn: 191758

Patch by Alp Toker.

llvm-svn: 191757

llvm-svn: 191756

llvm-svn: 191755

llvm-svn: 191754

llvm-svn: 191753

llvm-svn: 191752

llvm-svn: 191751

Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.

llvm-svn: 191750

Pointed out by Joerg.

llvm-svn: 191749

llvm-svn: 191748

llvm-svn: 191747

llvm-svn: 191746

llvm-svn: 191745

This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744

llvm-svn: 191743

llvm-svn: 191742

PR17425.

llvm-svn: 191741

llvm-svn: 191740

This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.

llvm-svn: 191739

Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.

llvm-svn: 191738

llvm-svn: 191737

llvm-svn: 191736

The old code skipped one of the sorting criteria if either pattern had
no types.  This could lead to cycles of the form X < Y, Y < Z, Z < X.

llvm-svn: 191735

This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.

llvm-svn: 191734