1. Jan 22, 2021
    • Walter Erquinigo's avatar
      [lldb-vscode] improve modules request · 39239f9b
      Walter Erquinigo authored
      lldb-vsdode was communicating the list of modules to the IDE with events, which in practice ended up having some drawbacks
      - when debugging large targets, the number of these events were easily 10k, which polluted the messages being transmitted, which caused the following: a harder time debugging the messages, a lag after terminated the process because of these messages being processes (this could easily take several seconds). The latter was specially bad, as users were complaining about it even when they didn't check the modules view.
      - these events were rarely used, as users only check the modules view when something is wrong and they try to debug things.
      
      After getting some feedback from users, we realized that it's better to not used events but make this simply a request and is triggered by users whenever they needed.
      
      This diff achieves that and does some small clean up in the existing code.
      
      Differential Revision: https://reviews.llvm.org/D94033
      39239f9b
    • David Green's avatar
      [LV][ARM] Inloop reduction cost modelling · 39db5753
      David Green authored
      This adds cost modelling for the inloop vectorization added in
      745bf6cf. Up until now they have been modelled as the original
      underlying instruction, usually an add. This happens to works OK for MVE
      with instructions that are reducing into the same type as they are
      working on. But MVE's instructions can perform the equivalent of an
      extended MLA as a single instruction:
      
        %sa = sext <16 x i8> A to <16 x i32>
        %sb = sext <16 x i8> B to <16 x i32>
        %m = mul <16 x i32> %sa, %sb
        %r = vecreduce.add(%m)
        ->
        R = VMLADAV A, B
      
      There are other instructions for performing add reductions of
      v4i32/v8i16/v16i8 into i32 (VADDV), for doing the same with v4i32->i64
      (VADDLV) and for performing a v4i32/v8i16 MLA into an i64 (VMLALDAV).
      The i64 are particularly interesting as there are no native i64 add/mul
      instructions, leading to the i64 add and mul naturally getting very
      high costs.
      
      Also worth mentioning, under NEON there is the concept of a sdot/udot
      instruction which performs a partial reduction from a v16i8 to a v4i32.
      They extend and mul/sum the first four elements from the inputs into the
      first element of the output, repeating for each of the four output
      lanes. They could possibly be represented in the same way as above in
      llvm, so long as a vecreduce.add could perform a partial reduction. The
      vectorizer would then produce a combination of in and outer loop
      reductions to efficiently use the sdot and udot instructions. Although
      this patch does not do that yet, it does suggest that separating the
      input reduction type from the produced result type is a useful concept
      to model. It also shows that a MLA reduction as a single instruction is
      fairly common.
      
      This patch attempt to improve the costmodelling of in-loop reductions
      by:
       - Adding some pattern matching in the loop vectorizer cost model to
         match extended reduction patterns that are optionally extended and/or
         MLA patterns. This marks the cost of the reduction instruction correctly
         and the sext/zext/mul leading up to it as free, which is otherwise
         difficult to tell and may get a very high cost. (In the long run this
         can hopefully be replaced by vplan producing a single node and costing
         it correctly, but that is not yet something that vplan can do).
       - getExtendedAddReductionCost is added to query the cost of these
         extended reduction patterns.
       - Expanded the ARM costs to account for these expanded sizes, which is a
         fairly simple change in itself.
       - Some minor alterations to allow inloop reduction larger than the highest
         vector width and i64 MVE reductions.
       - An extra InLoopReductionImmediateChains map was added to the vectorizer
         for it to efficiently detect which instructions are reductions in the
         cost model.
       - The tests have some updates to show what I believe is optimal
         vectorization and where we are now.
      
      Put together this can greatly improve performance for reduction loop
      under MVE.
      
      Differential Revision: https://reviews.llvm.org/D93476
      39db5753
    • Sanjay Patel's avatar
      [SLP] rename reduction variable to avoid shadowing; NFC · 2f03528f
      Sanjay Patel authored
      The code structure can likely be improved now that
      'OperationData' is gone.
      2f03528f
    • Anton Rapetov's avatar
      Scalar: Don't visit constants in findInnerReductionPhi in LoopInterchange · bfec9148
      Anton Rapetov authored
      In LoopInterchange, `findInnerReductionPhi()` looks for reduction
      variables, which cannot be constants. Update it to return early in that
      case.
      
      This also addresses a blocker for removing use-lists from ConstantData,
      whose users could be spread across arbitrary modules in the same
      LLVMContext.
      
      Differential Revision: https://reviews.llvm.org/D94712
      bfec9148
    • Christian Sigg's avatar
      Remove deprecated methods from OpState. · 8827e07a
      Christian Sigg authored
      Reviewed By: rriddle
      
      Differential Revision: https://reviews.llvm.org/D95123
      8827e07a
    • Duncan P. N. Exon Smith's avatar
      ADT: Fix reference invalidation in SmallVector::emplace_back and assign(N,V) · d7ff0036
      Duncan P. N. Exon Smith authored
      This fixes the final (I think?) reference invalidation in `SmallVector`
      that we need to fix to align with `std::vector`. (There is still some
      left in the range insert / append / assign, but the standard calls that
      UB for `std::vector` so I think we don't care?)
      
      For POD-like types, reimplement `emplace_back()` in terms of
      `push_back()`, taking a copy even for large `T` rather than lose the
      realloc optimization in `grow_pod()`.
      
      For other types, split the grow operation in three and construct the new
      element in the middle.
      
      - `mallocForGrow()` calculates the new capacity and returns the result
        of `safe_malloc()`. We only need a single definition per
        `SmallVectorBase` so this is defined in SmallVector.cpp to avoid code
        size bloat. Moving this part of non-POD grow to the source file also
        allows the logic to be easily shared with `grow_pod`, and
        `report_size_overflow()` and `report_at_maximum_capacity()` can move
        there too.
      - `moveElementsForGrow()` moves elements from the old to the new
        allocation.
      - `takeAllocationForGrow()` frees the old allocation and saves the
        new allocation and capacity .
      
      `SmallVector:assign(size_type, const T&)` also uses the split-grow
      operations for non-POD, but it also has a semantic change when not
      growing. Previously, assign would start with `clear()`, and so the old
      elements were destructed and all elements of the new vector were
      copy-constructed (potentially invalidating references). The new
      implementation skips destruction and uses copy-assignment for the prefix
      of the new vector that fits. The new semantics match what libc++ does
      for `std::vector::assign()`.
      
      Note that the following is another possible implementation:
      ```
        void assign(size_type NumElts, ValueParamT Elt) {
          std::fill_n(this->begin(), std::min(NumElts, this->size()), Elt);
          this->resize(NumElts, Elt);
        }
      ```
      The downside of this simpler implementation is that if the vector has to
      grow there will be `size()` redundant copy operations.
      
      (I had planned on splitting this patch up into three for committing
      (after getting performance numbers / initial review), but I've realized
      that if this does for some reason need to be reverted we'll probably
      want to revert the whole package...)
      
      Differential Revision: https://reviews.llvm.org/D94739
      d7ff0036
    • Michael Munday's avatar
      Recommit "[RISCV] Legalize select when Zbt extension available" · 4ab0f51a
      Michael Munday authored
      This recommits 71ed4b6c with
      the polarity of some of the pattern corrected.
      
      Original commit message:
      The custom expansion of select operations in the RISC-V backend
      interferes with the matching of cmov instructions. Legalizing
      select when the Zbt extension is available solves that problem.
      
      Reviewed By: luismarques, craig.topper
      
      Differential Revision: https://reviews.llvm.org/D93767
      4ab0f51a
    • Sanjay Patel's avatar
      [SLP] simplify reduction matching · d7775338
      Sanjay Patel authored
      This is NFC-intended and removes the "OperationData"
      class which had become nothing more than a recurrence
      (reduction) type.
      
      I adjusted the matching logic to distinguish
      instructions from non-instructions - that's all that
      the "IsLeafValue" member was keeping track of.
      d7775338
    • Bob Haarman's avatar
      [ELF] report section sizes when output file too large · 8e0b1793
      Bob Haarman authored
      Fixes PR48523. When the linker errors with "output file too large",
      one question that comes to mind is how the section sizes differ from
      what they were previously. Unfortunately, this information is lost
      when the linker exits without writing the output file. This change
      makes it so that the error message includes the sizes of the largest
      sections.
      
      Reviewed By: MaskRay, grimar, jhenderson
      
      Differential Revision: https://reviews.llvm.org/D94560
      8e0b1793
    • Nikita Popov's avatar
      [FunctionAttrs] Infer willreturn for functions without loops · 65fd034b
      Nikita Popov authored
      If a function doesn't contain loops and does not call non-willreturn
      functions, then it is willreturn. Loops are detected by checking
      for backedges in the function. We don't attempt to handle finite
      loops at this point.
      
      Differential Revision: https://reviews.llvm.org/D94633
      65fd034b
    • Duncan P. N. Exon Smith's avatar
      X86: Fix use-after-realloc in X86AsmParser::ParseIntelExpression · f2fd41d7
      Duncan P. N. Exon Smith authored
      `X86AsmParser::ParseIntelExpression` has a while loop. In the body,
      calls to MCAsmLexer::UnLex can force a reallocation in the MCAsmLexer's
      `CurToken` SmallVector, invalidating saved references to
      `MCAsmLexer::getTok()`.
      
      `const MCAsmToken &Tok` is such a saved reference, and this moves it
      from outside the while loop to inside the body, fixing a
      use-after-realloc.
      
      `Tok` will still be reused across calls to `Lex()`, each of which
      effectively destroys and constructs the pointed-to token. I'm a bit
      skeptical of this usage pattern, but it seems broadly used in the
      X86AsmParser (and others) so I'm leaving it alone (for now).
      
      Somehow this bug was exposed by https://reviews.llvm.org/D94739,
      resulting in test failures in dot-operator related tests in
      llvm/test/tools/llvm-ml. I suspect the exposure path is related to
      optimizer changes from splitting up the grow operation, but I haven't
      dug all the way in. Regardless, there are already tests in tree that
      cover this; they might fail consistently if we added ASan
      instrumentation to SmallVector.
      
      Differential Revision: https://reviews.llvm.org/D95112
      f2fd41d7
    • Joseph Huber's avatar
      [OpenMP] Fix failing test due to change in offloading flags · 119a9ea1
      Joseph Huber authored
      Summary:
      Prior to D91261 the information checked the OMP_MAP_TARGET_PARAM flag, change this as it has been removed. The INFO macro was changed to accept a flag as input to make conditionally printing information easier.
      
      Reviewed By: jdoerfert
      
      Differential Revision: https://reviews.llvm.org/D95133
      119a9ea1
    • Artem Belevich's avatar
      [CUDA] Normalize handling of defauled dtor. · 127091bf
      Artem Belevich authored
      Defaulted destructor was treated inconsistently, compared to other
      compiler-generated functions.
      
      When Sema::IdentifyCUDATarget() got called on just-created dtor which didn't
      have implicit __host__ __device__ attributes applied yet, it would treat it as a
      host function.  That happened to (sometimes) hide the error when dtor referred
      to a host-only functions.
      
      Even when we had identified defaulted dtor as a HD function, we still treated it
      inconsistently during selection of usual deallocators, where we did not allow
      referring to wrong-side functions, while it is allowed for other HD functions.
      
      This change brings handling of defaulted dtors in line with other HD functions.
      
      Differential Revision: https://reviews.llvm.org/D94732
      127091bf
    • peter klausler's avatar
      [flang] Better C_LOC and C_ASSOCIATED in flang/module · a75840a0
      peter klausler authored
      The place-holding implementation of C_LOC just didn't work
      when used with our more complete semantic checking, specifically
      in the case of a polymorphic argument; convert it to an external
      function with an implicit interface.  C_ASSOCIATED needs to be
      a generic interface with specific implementations for C_PTR and
      C_FUNPTR.
      
      Differential Revision: https://reviews.llvm.org/D94714
      a75840a0
    • Ulrich Weigand's avatar
      [NFC][Doc] Mention SystemZ supports StackMap generation · b3a5abcb
      Ulrich Weigand authored
      Support available as of commit 5eb64110.
      
      Differential Revision: https://reviews.llvm.org/D95040
      b3a5abcb
    • Hsiangkai Wang's avatar
      [RISCV] Update V instructions constraints to conform to v1.0 · b8921af6
      Hsiangkai Wang authored
      Upgrade RISC-V V extension to v1.0-08a0b46.
      Update instruction constraints to conform to v1.0.
      
      Differential Revision: https://reviews.llvm.org/D93612
      b8921af6
    • Giorgis Georgakoudis's avatar
      [OpenMP] Add time profiling support in libomp · 6b7645dd
      Giorgis Georgakoudis authored
      Profiling has been recently implemented in libomptarget (D93055). This patch enables time profiling support for libomptarget in libomp, to support profiling of multi-threaded execution of offloaded regions.
      
      Reviewed By: jdoerfert
      
      Differential Revision: https://reviews.llvm.org/D94855
      6b7645dd
    • Sebastian Neubauer's avatar
      Revert "[AMDGPU] Implement mir parseCustomPseudoSourceValue" · 4dbdff66
      Sebastian Neubauer authored
      This reverts commit ba7dcd85.
      
      (caused memory leaks)
      4dbdff66
    • Marek Kurdej's avatar
      [libc++] Use ioctl when available to get random_device entropy. · f3b979b6
      Marek Kurdej authored
      Implemented the idea from D94571 to improve entropy on Linux.
      
      Reviewed By: ldionne, #libc
      
      Differential Revision: https://reviews.llvm.org/D94953
      f3b979b6
    • Hsiangkai Wang's avatar
      [RISCV] Add new V instructions in v1.0-08a0b46. · 266820be
      Hsiangkai Wang authored
      Add new V instructions.
      vfrsqrte7.v
      vfrece7.v
      vrgatherei16.vv
      vneg.v
      vncvt.x.x.w
      vfneg.v
      266820be
    • Andrzej Warzynski's avatar
      [flang][driver] Move fixed/free from detection out of FrontendAction API · aba24c15
      Andrzej Warzynski authored
      All Fortran options should be set in `CompilerInstance` (via its
      `CompilerInvocation`) before any of `FrontendAction` is entered -
      that's one of the tasks of the driver. However, this is a bit tricky
      with fixed and free from detection introduced in
      https://reviews.llvm.org/D94228.
      
      Fixed-free form detection needs to happen:
        * before any frontend action (we need to specify `isFixedForm` in
          `Fortran::parser::Options` before running any actions)
        * separately for every input file (we might be compiling multiple
          Fortran files, some in free form, some in fixed form)
      In other words, we need this to happen early (before any
      `FrontendAction`), but not too early (we need to know what the current
      input file is). In practice, `isFixedForm` can only be set later
      than other options (other options are inferred from compiler flags). So
      we can't really set all of them in one place, which is not ideal.
      
      All changes in this patch are NFCs (hence no new tests). Quick summary:
        * move fixed/free form detection from `FrontendAction::ExecuteAction` to
          `CompilerInstance::ExecuteAction`
        * add a bool flag in `FrontendInputFile` to mark a file as fixed/free
          form
        * updated a few comments
      
      Differential Revision: https://reviews.llvm.org/D95042
      aba24c15
    • Hsiangkai Wang's avatar
      [RISCV] Make LMUL field in VTYPE continuous. · 9dd5aea1
      Hsiangkai Wang authored
      Upgrade RISC-V V extension to v1.0-08a0b46.
      Update the VTYPE encoding. Make LMUL encoding in a continuous field.
      9dd5aea1
  2. Jan 21, 2021