Differential Revision: https://reviews.llvm.org/D40981

llvm-svn: 320087

Patch caused a buildbot failure; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15733/steps/build_Lld/logs/stdio :
lib/Target/AMDGPU/SIInsertWaitcnts.cpp:396:11: error: private field 'InstCnt' is not used [-Werror,-Wunused-private-field]
  int32_t InstCnt = 0;
          ^
1 error generated.
"
This reverts commit 71627f79010aafe74fdcba901bba28dd7caa0869.

llvm-svn: 320086

requested by client

This is a follow up to r319702 which records parsing invocations.

These files are not emitted by default, and the client has to specify the
invocation emission path first.

rdar://35322543

llvm-svn: 320085

-amdgpu-waitcnt-forcezero={1|0}  Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-amdgpu-waitcnt-forceexp=<n>  Force emit a s_waitcnt expcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcevm=<n>   Force emit a s_waitcnt vmcnt(0) before the first <n> instrs

Differential Revision: https://reviews.llvm.org/D40091

llvm-svn: 320084

[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().

Differential Revision: https://reviews.llvm.org/D40098

llvm-svn: 320083

The current implementation of the nvptx runtime (to be upstreamed shortly) uses the atomicMax operation on 64-bit integers.
This is only supported in compute capabilities 3.5 and later. I've changed the clang default to sm_35.

Differential Revision: https://reviews.llvm.org/D40977

llvm-svn: 320082

[X86] Fix InsertBitToMaskVector to only issue KSHIFTS of native size so that upper bits are properly zeroed.

There's no v2i1 or v4i1 kshift, and v8i1 is only supported with AVXDQ. Isel has fake patterns to extend these types to native shifts, but makes no guarantees about the value of any bits shifted in when shifting right.

This patch promotes the vector to a type that supports a native shift first and only allows inserting into the msb of a native sized shift.

I've constructed this in a way that doesn't do the promotion if we're going to fallback to using a xmm/ymm/zmm shuffle. I think I have a plan to remove the shuffle fall back entirely. In which case we this can be simplified, but I wanted to fix the correctness issue first.

llvm-svn: 320081

llvm-svn: 320080

llvm-svn: 320079

Private variables are completely redefined in the outlined regions, so
we don't need to capture them. Patch adds this behavior to the
target-based regions.

llvm-svn: 320078

Mark them as such.

llvm-svn: 320077

This reverts commit 319790.

We worked around the bug in LLVM instead.

llvm-svn: 320076

Summary:
* use more readable name
* document the hwasan attribute

Reviewers: eugenis

Reviewed By: eugenis

Subscribers: llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D40938

llvm-svn: 320075

The constructor for ClangdLSPServer changed in r318412 and r318925,
breaking the clangd-fuzzer build.

llvm-svn: 320074

iOS/tvOS/watchOS simulator

rdar://35135215

Differential Revision: https://reviews.llvm.org/D40682

llvm-svn: 320073

llvm-svn: 320072

This part of lldb make use of anonymous structs and unions. The usage is
idiomatic and doesn't deserve a warning. Logic in the NSDictionary and NSSet
plugins use anonymous structs in a manner consistent with the relevant Apple
frameworks.

Differential Revision: https://reviews.llvm.org/D40757

llvm-svn: 320071

llvm-svn: 320070

With this memory usage when linking clang goes from 174.62MB to
172.77MB.

llvm-svn: 320069

llvm-svn: 320068

llvm-svn: 320067

They're hidden, so all they cause is a linker warning.

ld: warning: cannot export hidden symbol
lldb::SBBreakpointNameImpl::operator==(lldb::SBBreakpointNameImpl const&) from
tools/lldb/source/API/CMakeFiles/liblldb.dir/SBBreakpointName.cpp.o

llvm-svn: 320066

llvm-svn: 320065

Put these under UNARY/BINOP ALU itinerary classes for now - seems to be a good average value

llvm-svn: 320064

Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.

llvm-svn: 320063

llvm-svn: 320062

llvm-svn: 320061

llvm-svn: 320060

llvm-svn: 320059

llvm-svn: 320058

Should bring back the arm/arm64 bots. Reported by Yvan Roux.

llvm-svn: 320057

Summary:
I also changed the message to print both the ISA and the the architecture
name for incompatible files. Previously it would be quite hard to find the
actual path of the incompatible object files in projects that have many
object files with the same name in different directories.

Reviewers: atanasyan, ruiu

Reviewed By: atanasyan

Subscribers: emaste, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D40958

llvm-svn: 320056

Treat these the same as LAHF/SAHF (although its not a x86_64 instruction)

llvm-svn: 320055

llvm-svn: 320054

Tagged all as system instructions

llvm-svn: 320053

llvm-svn: 320052

Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well

llvm-svn: 320051

I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either 
repeating a scalar insertion at the same position in a vector or translated to a different 
element index.

Like the earlier patch, this could be an instcombine too, but since we opted to make this 
a DAG transform earlier, I've made this one a DAG patch too.

We do not need any legality checking because the new insert is identical to the existing 
insert except that it may have a different constant insertion operand.

The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the 
motivation for D38756.

Differential Revision: https://reviews.llvm.org/D40209

llvm-svn: 320050

Differential Revision: https://reviews.llvm.org/D40390

llvm-svn: 320049

llvm-svn: 320048