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r260588 | thomas.stellard | 2016-02-11 13:14:34 -0800 (Thu, 11 Feb 2016) | 20 lines

AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklist

Summary:
When we split SMRD instructions into two MUBUFs we were adding the users
of the newly created MUBUFs to the VALU worklist.  However, the only
users these instructions had was the REG_SEQUENCE that was inserted
by splitSMRD when the original SMRD instruction was split.

We need to make sure to add the users of the original SMRD to the VALU
worklist before it is split.

I have a test case, but it requires one other bug fix, so it will be
added in a later commt.

Reviewers: mareko, arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D17101

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llvm-svn: 271641

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r260495 | Matthew.Arsenault | 2016-02-10 22:15:39 -0800 (Wed, 10 Feb 2016) | 9 lines

AMDGPU: Fix constant bus use check with subregisters

If the two operands to an instruction were both
subregisters of the same super register, it would incorrectly
think this counted as the same constant bus use.

This fixes the verifier error in fmin_legacy.ll which
was missing -verify-machineinstrs.

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llvm-svn: 271640

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r259911 | Matthew.Arsenault | 2016-02-05 11:47:23 -0800 (Fri, 05 Feb 2016) | 5 lines

AMDGPU: Preserve alignments on new created globals

Also switch to internal linkage, and include the name of the function in
the name.

------------------------------------------------------------------------

llvm-svn: 271639

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r259894 | thomas.stellard | 2016-02-05 09:42:38 -0800 (Fri, 05 Feb 2016) | 8 lines

AMDGPU/SI: Correctly initialize SIInsertWaits pass

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16724

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llvm-svn: 271594

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r259558 | Matthew.Arsenault | 2016-02-02 12:28:10 -0800 (Tue, 02 Feb 2016) | 4 lines

AMDGPU: Handle promoting memmove

Also add missing tests for the others.

------------------------------------------------------------------------

llvm-svn: 271593

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r259546 | Matthew.Arsenault | 2016-02-02 11:18:53 -0800 (Tue, 02 Feb 2016) | 5 lines

AMDGPU: Whitelist handled intrinsics

We shouldn't crash on unhandled intrinsics.
Also simplify failure handling in loop.

------------------------------------------------------------------------

llvm-svn: 271592

We need to correctly initialize the AMDGPUPromoteAlloca pass, because
later commits will add tests that try to pass the -amdgpu-promote-alloca
flag to opt.

llvm-svn: 271591

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r259059 | thomas.stellard | 2016-01-28 09:13:44 -0800 (Thu, 28 Jan 2016) | 14 lines

AMDGPU: waitcnt operand fixes

Summary:
Allow lgkmcnt up to 0xF (hardware allows that).
Fix mask for ExpCnt in AMDGPUInstPrinter.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16314

Patch by: Nikolay Haustov

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llvm-svn: 271590

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r258936 | thomas.stellard | 2016-01-27 07:53:52 -0800 (Wed, 27 Jan 2016) | 14 lines

AMDGPU/SI: Fix commuting of 32-bit VOPC instructions

Summary:
We didn't have entries in the commuting table for the 32-bit
instructions.  I don't think we hit this problem now, but we
will once uniform branching is enabled.  Tests will come in
a later commit.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16600

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llvm-svn: 271589

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r258901 | Matthew.Arsenault | 2016-01-26 18:17:49 -0800 (Tue, 26 Jan 2016) | 17 lines

AMDGPU: Fix default device handling

When no device name is specified, default to kaveri
for HSA since SI is not supported and it woud fail.

Default to "tahiti" instead of "SI" since these are
effectively the same, and tahiti is an actual device.

Move default device handling to the TargetMachine
rather than the AMDGPUSubtarget. The module ISA version
is computed from the device name provided with the target
machine, so the attributes printed by the AsmPrinter were
inconsistent with those computed in the subtarget.

Also remove DevName field from subtarget since it's redundant
with getCPU() in the superclass.

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llvm-svn: 271588

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r258606 | Matthew.Arsenault | 2016-01-22 21:32:14 -0800 (Fri, 22 Jan 2016) | 5 lines

AMDGPU: Remove Feature64BitPtr

This is a leftover from AMDIL that doesn't do anything
and doesn't belong here.

------------------------------------------------------------------------

llvm-svn: 271587

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r271035 | hfinkel | 2016-05-27 14:04:05 -0500 (Fri, 27 May 2016) | 3 lines

Fix storing the frame pointer for OMP-T during ppc64 microtask dispatch

Thanks to John Mellor-Crummey for reporting the omission.
------------------------------------------------------------------------

llvm-svn: 271583

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r270884 | jlpeyton | 2016-05-26 13:19:10 -0500 (Thu, 26 May 2016) | 11 lines

Make LIBOMP_USE_ITT_NOTIFY a setting that can be enabled or disabled

On Blue Gene/Q, having LIBOMP_USE_ITT_NOTIFY support compiled into a
statically-linked binary causes a failure at runtime because dlopen fails.
This patch changes LIBOMP_USE_ITT_NOTIFY to a cacheable configuration setting
that can be disabled.

Patch by John Mellor-Crummey

Differential Revision: http://reviews.llvm.org/D20517

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llvm-svn: 271581

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r270821 | hfinkel | 2016-05-25 23:48:14 -0500 (Wed, 25 May 2016) | 6 lines

Add an assembly __kmp_invoke_microtask for ppc64[le]

Clang no longer restricts itself to generating microtasks with a small number
of arguments, and so an assembly implementation is required to prevent hitting
the parameter limit present in the C implementation. This adds an
implementation for ppc64[le].
------------------------------------------------------------------------

llvm-svn: 271580

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r270464 | jlpeyton | 2016-05-23 12:50:32 -0500 (Mon, 23 May 2016) | 12 lines

Allow unit testing on Windows

These changes allow testing on Windows using clang.exe.
There are two main changes:
1. Only link to -lm when it actually exists on the system
2. Create basic versions of pthread_create() and pthread_join() for windows.
   They are not POSIX compliant by any stretch but will allow any existing
   and future tests to use pthread_create() and pthread_join() for testing
   interactions of libomp with os threads.

Differential Revision: http://reviews.llvm.org/D20391

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llvm-svn: 271578

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r258607 | Matthew.Arsenault | 2016-01-22 21:32:18 -0800 (Fri, 22 Jan 2016) | 4 lines

AMDGPU: Remove IntrNoMem from llvm.SI.sendmsg

This has side effects.

------------------------------------------------------------------------

llvm-svn: 271485

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r258537 | Matthew.Arsenault | 2016-01-22 11:47:54 -0800 (Fri, 22 Jan 2016) | 6 lines

AMDGPU: Fix crash with invariant markers

The promote alloca pass didn't handle these intrinsics and crashed.
These intrinsics should accept any address space, but for now just
erase them to avoid breaking.

------------------------------------------------------------------------

llvm-svn: 271484

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r258319 | thomas.stellard | 2016-01-20 07:48:27 -0800 (Wed, 20 Jan 2016) | 8 lines

Correctly initialize SIAnnotateControlFlow

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16304

------------------------------------------------------------------------

llvm-svn: 271483

llvm-svn: 271395

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r261430 | joerg | 2016-02-20 12:24:44 +0100 (Sat, 20 Feb 2016) | 15 lines

When MemoryDependenceAnalysis hits a CFG with many transparent blocks,
the algorithm easily degrades into quadratic memory and time complexity.
The easiest example is a long chain of BBs that don't otherwise use a
location. The caching will add an entry for every intermediate block and
limiting the number of results doesn't help as no results are produced
until a definition is found.

Introduce a limit similar to the existing instructions-per-block limit.
This limit counts the total number of blocks checked. If the limit is
reached, entries are considered unknown. The initial value is 1000,
which avoids regressions for normal sized functions while still
limiting edge cases to reasnable memory consumption and execution time.

Differential Revision: http://reviews.llvm.org/D16123

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llvm-svn: 271394

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r270564 | slthakur | 2016-05-24 20:22:50 +0530 (Tue, 24 May 2016) | 9 lines

[LLDB][MIPS] Fix floating point handling in case of thread step-out

Patch by Nitesh Jain.

Summary: These patch fix thread step-out for hard and soft float.

Reviewers: jaydeep, bhushan, clayborg
Differential Revision: http://reviews.llvm.org/D20416

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llvm-svn: 271390

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r270208 | slthakur | 2016-05-20 17:41:52 +0530 (Fri, 20 May 2016) | 10 lines

[LLDB][MIPS] Fix Floating point Registers Encoding

Patch by Nitesh Jain.

Summary: Currently floating point regsiters has eEncodingUint encoding. Hence register write  '1.25' will failed. This patch add eEncodingIEEE754 encoding for floating point registers( - ). This patch will fix test_fp_register_write in TestRegisters.py

Reviewers: clayborg, sagar
Subscribers: mohit.bhakkad, jaydeep, bhushan, sdardis, lldb-commits
Differential: D18853

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llvm-svn: 271383

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r269407 | slthakur | 2016-05-13 16:34:47 +0530 (Fri, 13 May 2016) | 10 lines

[LLDB][MIPS] Provide ABI string to compiler for appropriate code generation for MIPS

Patch by Nitesh Jain.

Summary: These patch will set clang::TargetOptions::ABI and accordingly code will be generated for MIPS target.

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, jaydeep, bhushan
Differential: D18638

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llvm-svn: 271381

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r269181 | slthakur | 2016-05-11 18:38:29 +0530 (Wed, 11 May 2016) | 10 lines

[LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI

Patch by Nitesh Jain.

Summary: The ArchSpec::m_flags will be set based on ELF flag ABI.

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, jaydeep, bhushan
Differential: D18858

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llvm-svn: 271379

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r261206 | bhushan.attarde | 2016-02-18 17:23:28 +0530 (Thu, 18 Feb 2016) | 9 lines

[LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
    
    SUMMARY:
    This patch implements ArchSpec::GetClangTargetCPU() that provides string representing current architecture as a target CPU.
    This string is then passed to tools like clang so that they generate correct code for that target.
    
    Reviewers: clayborg, zturner
    Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
    Differential Revision: http://reviews.llvm.org/D17022
------------------------------------------------------------------------

llvm-svn: 271378

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r263621 | mohit.bhakkad | 2016-03-16 13:53:10 +0530 (Wed, 16 Mar 2016) | 9 lines

[ASAN] Add support for mips/mips64 android

Patch by Duane Sand

Reviewers: samsonov

Subscribers: duanesand, jaydeep, sagar, llvm-commits, filcab.

Differential Revision: http://reviews.llvm.org/D17883
------------------------------------------------------------------------

llvm-svn: 271372

[r260944] clang-tools-extra/test/Unit/lit.site.cfg.in: Prune on_clone. I guess it has been unused since r188006.

llvm-svn: 271354

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r261139 | deadalnix | 2016-02-17 11:21:28 -0800 (Wed, 17 Feb 2016) | 10 lines

Fix load alignement when unpacking aggregates structs

Summary: Store and loads unpacked by instcombine do not always have the
right alignement. This explicitely compute the alignement and set it.

Reviewers: dblaikie, majnemer, reames, hfinkel, joker.eph

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17326

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llvm-svn: 271230

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r270550 | rafael | 2016-05-24 12:16:14 +0100 (Tue, 24 May 2016) | 1 line

Update for llvm change.
------------------------------------------------------------------------
The referenced llvm change was r270542.

llvm-svn: 271223

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r266438 | niravd | 2016-04-15 08:01:38 -0700 (Fri, 15 Apr 2016) | 15 lines

Fix typing on generated LXV2DX/STXV2DX instructions

[PPC] Previously when casting generic loads to LXV2DX/ST instructions we
would leave the original load return type in place allowing for an
assertion failure when we merge two equivalent LXV2DX nodes with
different types.

This fixes PR27350.

Reviewers: nemanjai

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D19133

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llvm-svn: 271217

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r266217 | niravd | 2016-04-13 10:27:26 -0700 (Wed, 13 Apr 2016) | 12 lines

Cleanup Store Merging in UseAA case

This patch fixes a bug (PR26827) when using anti-aliasing in store
merging. This sets the chain users of the component stores to point to
the new store instead of the component stores chain parent.

Reviewers: jyknight

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18909

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llvm-svn: 271216

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r263428 | zbuljan | 2016-03-14 12:50:23 +0000 (Mon, 14 Mar 2016) | 3 lines

[mips] Fix an issue with long double when function roundl is defined
Differential Revision: http://reviews.llvm.org/D17760

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llvm-svn: 271127

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r262230 | vkalintiris | 2016-02-29 15:58:12 +0000 (Mon, 29 Feb 2016) | 7 lines

[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15420
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llvm-svn: 271126

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r268386 | dsanders | 2016-05-03 15:19:26 +0100 (Tue, 03 May 2016) | 11 lines

[mips][fastisel] ADJCALLSTACKUP has a second immediate operand.

Summary:
It's always zero for SelectionDAG and is never read by the MIPS backend so
do the same for FastISel.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19863
------------------------------------------------------------------------

llvm-svn: 271124

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r268053 | sdardis | 2016-04-29 17:07:47 +0100 (Fri, 29 Apr 2016) | 9 lines

[mips][FastISel] A store is not a load.

Correct trivial error. One of the failing tests from PR/27458.

Reviewers: dsanders, vkalintiris, mcrosier

Differential Review: http://reviews.llvm.org/D19726


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llvm-svn: 271123

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r259039 | zjovanovic | 2016-01-28 11:08:03 +0000 (Thu, 28 Jan 2016) | 9 lines

[mips][microMIPS] Disable FastISel for microMIPS

Author: milena.vujosevic.janicic
Reviewers: dsanders

FastIsel is not supported for microMIPS, thus it needs to be disabled. 
Test micromips-zero-mat-uses.ll is deleted since the tested sequence of instructions is not generated for microMIPS without FastISel.
Differential Revision: http://reviews.llvm.org/D15892

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llvm-svn: 271122

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r268673 | koriakin | 2016-05-05 21:13:17 +0100 (Thu, 05 May 2016) | 5 lines

[MSan] [MIPS64] Fix vararg helper for >1 fixed argument.

This fixes http://llvm.org/PR27646 on Mips64.

Differential Revision: http://reviews.llvm.org/D19989
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llvm-svn: 271121

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r268531 | koriakin | 2016-05-04 19:39:14 +0100 (Wed, 04 May 2016) | 3 lines

[MSan] [Mips64] Add tests for vararg handling.

Differential Revision: http://reviews.llvm.org/D19919
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llvm-svn: 271120

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r266833 | koriakin | 2016-04-20 00:46:59 +0100 (Wed, 20 Apr 2016) | 5 lines

[Mips] [MSan] VarArgMIPS64Helper: Use target's endian, not host's.

Ugh.

Differential Revision: http://reviews.llvm.org/D19292
------------------------------------------------------------------------

llvm-svn: 271119

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r270542 | slthakur | 2016-05-24 15:27:10 +0530 (Tue, 24 May 2016) | 9 lines

[MIPS][LLVM-MC] Fix Disassemble of Negative Offset

Patch by Nitesh Jain.

Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added.

Reviewers: dsanders, vkalintiris
Differential Revision: http://reviews.llvm.org/D17540

------------------------------------------------------------------------

llvm-svn: 270676