AF = dyn_cast<SCEVAddRecExpr>(Pair.second) may be NULL for some SCEVs that we do
not support. When reporting the error we still want to pass a pointer that is
known to always be non-NULL.

I do not yet have a test case for this, unfortunately.

llvm-svn: 225461

strings from the copies that remain.

llvm-svn: 225460

than a pointer to make unifying code a bit easier.

llvm-svn: 225459

only the subtarget.

llvm-svn: 225458

llvm-svn: 225457

llvm-svn: 225456

llvm-svn: 225455

llvm-svn: 225454

It now checks for the end of the line or the opening '{'.
While at it, remove empty comments.

llvm-svn: 225451

Summary: The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register).  This does that.

Test Plan: Tests updated.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6876

llvm-svn: 225450

llvm-svn: 225449

llvm-svn: 225448

- includes header/footer as required by MELPA
- correctly handles buffers that are not associated with a file
- displays stderr and exit code of clang-format process
- customizable via the emacs customization interface and file-/directory-
  local variables

Patch by Johann Klähn.

llvm-svn: 225447

This partially fixes PR13007 (ARM CodeGen fails with large stack
alignment): for ARM and Thumb2 targets, but not for Thumb1, as it
seems stack alignment for Thumb1 targets hasn't been supported at
all.

Producing an aligned stack pointer is done by zero-ing out the lower
bits of the stack pointer. The BIC instruction was used for this.
However, the immediate field of the BIC instruction only allows to
encode an immediate that can zero out up to a maximum of the 8 lower
bits. When a larger alignment is requested, a BIC instruction cannot
be used; llvm was silently producing incorrect code in this case.

This commit fixes code generation for large stack aligments by
using the BFC instruction instead, when the BFC instruction is
available.  When not, it uses 2 instructions: a right shift,
followed by a left shift to zero out the lower bits.

The lowering of ARM::Int_eh_sjlj_dispatchsetup still has code
that unconditionally uses BIC to realign the stack pointer, so it
very likely has the same problem. However, I wasn't able to
produce a test case for that. This commit adds an assert so that
the compiler will fail the assert instead of silently generating
wrong code if this is ever reached.

llvm-svn: 225446

Its functionality has been replaced by calling
SIInstrInfo::legalizeOperands() from
SIISelLowering::AdjstInstrPostInstrSelection() and running the
SIFoldOperands and SIShrinkInstructions passes.

llvm-svn: 225445

This makes piped output easier to read in many instances.

Before:
  llvm::errs() << aaaa << std::endl << bbbb << std::endl;

After:
  llvm::errs() << aaaa << std::endl
               << bbbb << std::endl;

Also fix a few instance of "don't use else after return" as per the
coding standards.

llvm-svn: 225444

Differential Revision: http://reviews.llvm.org/D6825

llvm-svn: 225443

If there are some non-ascii character in the input source code, the
column index might be smallar than the byte index.  This will result
in two possible assertion failures.  This CL fixes the computation of
the column index and byte index.

1. The assertion in startOfNextColumn() and startOfPreviousColumn()
   should not be raised when the byte index is greater than the column
   index since the non-ascii characters may use more than one bytes to
   store a character in a column.

2. The length of the caret line should be equal to the number of columns
   of source line, instead of the length of the source line.  Otherwise,
   the assertion in selectInterestingSourceRegion will be raised because
   the removed columns plus the kept columns are not greater than the max
   column, which means that we should not remove any column at all.

llvm-svn: 225442

llvm-svn: 225441

llvm-svn: 225440

llvm-svn: 225439

The call lowering assumes that if the callee is a global, we want to emit a direct call.
This is correct for regular globals, but not for TLS ones.

Differential Revision: http://reviews.llvm.org/D6862

llvm-svn: 225438

PEI tries to keep track of how much starting or ending a call sequence adjusts the stack pointer by, so that it can resolve frame-index references. Currently, it takes a very simplistic view of how SP adjustments are done - both FrameStartOpcode and FrameDestroyOpcode adjust it exactly by the amount written in its first argument.

This view is in fact incorrect for some targets (e.g. due to stack re-alignment, or because it may want to adjust the stack pointer in multiple steps). However, that doesn't cause breakage, because most targets (the only in-tree exception appears to be 32-bit ARM) rely on being able to simplify the call frame pseudo-instructions earlier, so this code is never hit. 

Moving the computation into TargetInstrInfo allows targets to override the way the adjustment is computed if they need to have a non-zero SPAdj.

Differential Revision: http://reviews.llvm.org/D6863

llvm-svn: 225437

Patch by Bhushan Attarde

Reviewers: clayborg

Reviewed By: clayborg

Subscribers: petarj, dsanders, mohit.bhakkad, lldb-commits

Differential Revision: http://reviews.llvm.org/D6861

llvm-svn: 225436

Before:
  struct A < std::enable_if<sizeof(T2) <sizeof(int32)>::type>;

After:
  struct A<std::enable_if<sizeof(T2) < sizeof(int32)>::type>;

llvm-svn: 225435

llvm-svn: 225434

Summary:
    With this patch, llgo uses ssautil.Switches
    to reconstitute (and synthesise) switches,
    which can then be lowered to lookup tables,
    trees, etc.

    We currently only handle integer const case
    switches. We erase the comparison blocks (other
    than the initial block), and generate a switch
    instruction at the end of the block starting
    the if-else-if chain. ssautil.Switches does
    not remove duplicate const cases (e.g. same
    operands for "||"), so we do this in llgo for
    now.

Test Plan: lit test added

Reviewers: pcc

Reviewed By: pcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6831

llvm-svn: 225433

[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.

llvm-svn: 225432

which registers have been spilled (saved to the stack) - and
if we see that same register being saved to the stack again,
don't record that, it's something specific to this stack frame.

I found a code sequence for i386 where clang did a push %esi
and then later in the function it did movl %esi, -0x7c(%ebp)
and that second save of a scratch value overrode the original
push location.

<rdar://problem/19171178> 

llvm-svn: 225431

In early C++11 standard drafts, std::function derived from std::unary_function or std::binary_function if there was only one (or two) parameters. Before C++11 shipped, this restiction was lifted, but libc++ still does this (which is fine). However, the tests still check for this outdated requiremnt. Change then to check for the nested typedefs instead (which are still required by the standard). No change to the library.

llvm-svn: 225430

llvm-svn: 225429

This is necessary to support linking a basic program which references symbols
outside of the module itself.  Add the import thunk for ARM NT style imports.
This allows us to create the reference.  However, it is still insufficient to
generate executables that will run due to base relocations not being emitted for
the import.

llvm-svn: 225428

so that we will use the UnwindPlan's rule for providing the stack
pointer BEFORE we use the trick of using the callee's CFA address
as the stack pointer.  When we're in a _sigtramp frame, the CFA of
the _sigtramp stack frame is not the same as the stack pointer value
when the async interrupt occurred -- we need to use the eh_frame
rules for retrieving the correct value.

<rdar://problem/18913548> 

llvm-svn: 225427

llvm-svn: 225426

Differential Revision: http://reviews.llvm.org/D6669

Submitted for Chaoren Lin

llvm-svn: 225425

This reverts commit r225379 while investigating an assertion failure reported
by Alexey.

llvm-svn: 225424

unprintable characters.  Fixes PR22048.

llvm-svn: 225423

A broken hint is a copy where both ends are assigned different colors. When a
variable gets evicted in the neighborhood of such copies, it is likely we can
reconcile some of them.


** Context **

Copies are inserted during the register allocation via splitting. These split
points are required to relax the constraints on the allocation problem. When
such a point is inserted, both ends of the copy would not share the same color
with respect to the current allocation problem. When variables get evicted,
the allocation problem becomes different and some split point may not be
required anymore. However, the related variables may already have been colored.

This usually shows up in the assembly with pattern like this:
def A
...
save A to B
def A
use A
restore A from B
...
use B

Whereas we could simply have done:
def B
...
def A
use A
...
use B


** Proposed Solution **

A variable having a broken hint is marked for late recoloring if and only if
selecting a register for it evict another variable. Indeed, if no eviction
happens this is pointless to look for recoloring opportunities as it means the
situation was the same as the initial allocation problem where we had to break
the hint.

Finally, when everything has been allocated, we look for recoloring
opportunities for all the identified candidates.
The recoloring is performed very late to rely on accurate copy cost (all
involved variables are allocated).
The recoloring is simple unlike the last change recoloring. It propagates the
color of the broken hint to all its copy-related variables. If the color is
available for them, the recoloring uses it, otherwise it gives up on that hint
even if a more complex coloring would have worked.

The recoloring happens only if it is profitable. The profitability is evaluated
using the expected frequency of the copies of the currently recolored variable
with a) its current color and b) with the target color. If a) is greater or
equal than b), then it is profitable and the recoloring happen.


** Example **

Consider the following example:
BB1:
  a =
  b =
BB2:
  ...
   = b
   = a
Let us assume b gets split:
BB1:
  a =
  b =
BB2:
  c = b
  ...
  d = c
  = d
  = a
Because of how the allocation work, b, c, and d may be assigned different
colors. Now, if a gets evicted to make room for c, assuming b and d were
assigned to something different than a.
We end up with:
BB1:
  a =
  st a, SpillSlot
  b =
BB2:
  c = b
  ...
  d = c
  = d
  e = ld SpillSlot
  = e
This is likely that we can assign the same register for b, c, and d,
getting rid of 2 copies.


** Performances **

Both ARM64 and x86_64 show performance improvements of up to 3% for the
llvm-testsuite + externals with Os and O3. There are a few regressions too that
comes from the (in)accuracy of the block frequency estimate.

<rdar://problem/18312047>

llvm-svn: 225422

type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532

llvm-svn: 225421

llvm-svn: 225420