Skip to content
GitLab
Commit f22aa8f8 authored by Craig Topper's avatar Craig Topper
Browse files

[RISCV] Add test cases for missed opportunities to use *W instructions for... 

[RISCV] Add test cases for missed opportunities to use *W instructions for div/rem when inputs are sign/zero extended from i8/16 instead of i32.
parent 60ebf640
Hide whitespace changes
Inline Side-by-side
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment