[RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, c3-c2), c3). (#91638)
Where c1 is a shifted mask with 32 set bits and c3 trailing zeros.
parent
5a0e0b65
Please register or sign in to comment
Where c1 is a shifted mask with 32 set bits and c3 trailing zeros.