Commit df722b01 authored by sstwcw's avatar sstwcw
Browse files

[clang-format] Don't indent Verilog `begin` keyword on its own line

When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149657
parent e1242855
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