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Unverified Commit c8dc6b59 authored by Yingwei Zheng's avatar Yingwei Zheng Committed by GitHub
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[SDAG] Improve `SimplifyDemandedBits` for mul (#90034) 

If the RHS is a constant with X trailing zeros, then the X MSBs of the
LHS are not demanded.

Alive2: https://alive2.llvm.org/ce/z/F5CyJW
Fixes https://github.com/llvm/llvm-project/issues/56645.
parent 831d1435
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