Merging r367019:

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r367019 | chill | 2019-07-25 15:56:04 +0200 (Thu, 25 Jul 2019) | 10 lines

[AArch64][SVE] Allow explicit size specifier for predicate operand

... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue
supporting the exsting behaviour of not requiring an explicit size
specifier. The preferred disasembly is *with* the specifier.

This is implemented by redefining intruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.

Differential Revision: https://reviews.llvm.org/D65145
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llvm-svn: 369086