[RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32
In our default SelectionDAG where i32 isn't legal, the zext will become and i64 AND and often get optimized out on its own. With i32 legal, we need to turn it in into sext.w and rely on RISCVOptWInstrs to remove it.
parent
05300222
Please register or sign in to comment