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Commit 78b75b45 authored by Jingu Kang's avatar Jingu Kang
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[AArch64] Add TableGen patterns to generate uaddlv 

uaddv(uaddlp(x)) ==> uaddlv(x)
addp(uaddlp(x))  ==> uaddlv(x)

Differential Revision: https://reviews.llvm.org/D104236
parent 836992ab
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