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Unverified Commit 6f5b372d authored by Matthew Devereau's avatar Matthew Devereau Committed by GitHub
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[AArch64][SME2][SVE2p1] Add PNR_3b regclass (#67785) 

This patch adds the PNR_3b regclass for predicate-as-counter registers
0-7 and allows the Upl ASM constraint to use this register class.
parent 8a2fb139
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