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Commit 54aeaa2a authored by Simon Pilgrim's avatar Simon Pilgrim
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[X86] Ensure 256-bit sqrt + crosslane shuffles are set to 2 uops + half rate 

Fixes another mismatch between the D103695 script and the znver1 scheduler model

Confirmed with the AMD SoG, Agner + instlatx64
parent f5831179
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