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Unverified Commit 50df08cd authored by chuongg3's avatar chuongg3 Committed by GitHub
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[GlobalISel][AArch64] Combine Vector Reduction Add Long (#76241) 

ADDLV(ADDLP) => ADDLV
Removes unnecessary ADDLP instruction
Already exists for SDAG, adding for GlobalISel
parent a43c1925
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