[RISCV] Add sched model for XiangShan-NanHu (#70232)

[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an
open-source high-performance RISC-V processor.

This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of
the XiangShan processor series.
Overview:
https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/

It is based on the patch [D122556](https://reviews.llvm.org/D122556

) by
@SForeKeeper. The original patch hasn't been updated for a long time and
it is out of sync with the current RTL design.

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Co-authored-by: SForeKeeper <zkliu6@gmail.com>