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Unverified Commit 1fe7bdb8 authored by Shengchen Kan's avatar Shengchen Kan Committed by GitHub
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[X86][CodeGen] Support lowering for NDD ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT/INC/DEC/IMUL (#77564) 

We supported encoding/decoding for these instructions in

https://github.com/llvm/llvm-project/pull/76319
https://github.com/llvm/llvm-project/pull/76721
https://github.com/llvm/llvm-project/pull/76919
parent 9ed30012
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