Unverified Commit 10c2d5ff authored by Jiahan Xie's avatar Jiahan Xie Committed by GitHub
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[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.
parent 41be5412
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