- May 15, 2014
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Shaik Ameer Basha authored
This patch includes, 1] renaming of the HSI2C clocks 2] renaming of spi clocks according to the datasheet 3] fixes for child-parent relationships 4] adding of more clocks related to PERIC block 5] use GATE_IP_* offsets instead of GATE_BUS_* Signed-off-by:Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by:
Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com>
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Shaik Ameer Basha authored
This patch corrects some child-parent clock relationships, and updates the clocks according to the latest datasheet. Signed-off-by:
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Shaik Ameer Basha authored
This patch adds missing clocks of G2D block. It also removes the aclkg3d alias from G3D block clocks. Signed-off-by:
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Shaik Ameer Basha authored
This patch fixes the parent clocks for mscl sysmmu. Signed-off-by:
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Shaik Ameer Basha authored
This patch adds the missing GSCL and MSCL block clocks and corrects some wrong parent-child relationships. Signed-off-by:
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Shaik Ameer Basha authored
This patch adds minimum set of clocks to gate ISP block for power saving. Signed-off-by:
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Shaik Ameer Basha authored
This patch renames the mux parent arrays as per the naming convension followed by the other exynos specific clock drivers. And it also renames "mout_cpu_kfc" clock to "mout_kfc". Signed-off-by:
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Arun Kumar K authored
Adds IDs for the clocks needed by the ARM Mali GPU in exynos5420. Signed-off-by:
Arun Kumar K <arun.kk@samsung.com> Signed-off-by:
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Tomasz Stanislawski authored
Export sclk_hdmiphy clock to be usable from DT. Signed-off-by:
Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by:
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Arun Kumar K authored
This patch adds the required clocks for ARM Mali IP in Exynos5250. Signed-off-by:
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Sylwester Nawrocki authored
Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs. Suggested-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
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Pankaj Dubey authored
When compiled using ARM64 cross compiler, gcc complains as drivers/clk/samsung/clk.c:293:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by:
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Sachin Kamat authored
Set it as per the user manual. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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Naveen Krishna Chatradhi authored
This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by:
Naveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by:
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Tomasz Figa authored
Before this patch, the driver was simply zeroing the clock table, which is incorrect, because invalid clock numbers returned NULL instead of error pointers. This patch fixes this by changing the driver to initialize the array with PTR_ERR(-ENOENT). Signed-off-by:
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Rahul Sharma authored
Add support for exynos5260 clocks in clock driver. Signed-off-by:
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Rahul Sharma authored
Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks. Signed-off-by:
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Rahul Sharma authored
Add support for pll2650xx in samsung pll file. This PLL variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by:
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Pankaj Dubey authored
exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by:
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Rahul Sharma authored
Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by:
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- May 13, 2014
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Heiko Stuebner authored
This finally removes all remaining SAMSUNG_CLOCK conditional code from s3c24xx architectures. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Heiko Stuebner authored
With the move to the common clock framework completed for s3c2410, s3c2440 and s3c2442, the legacy clock code for these machines can go away too. This also includes the legacy dclk code, as all legacy users are converted. Signed-off-by:
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Heiko Stuebner authored
Convert the machines using the s3c2410 to use the new driver based on the common clock framework instead of the legacy Samsung clock driver. As with the s3c244x, machines using the clkout output will need a fixup from someone with the hardware. Signed-off-by:
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Heiko Stuebner authored
Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Some of the more esotheric machines will probably need a fixup, as they do strange things to the clkout outputs, that I did not really understand nor have the hardware to check. Signed-off-by:
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Heiko Stuebner authored
This adds the necessary init functions to init the clocks from the common clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy clock code. This also includes empty stubs for the *_setup_clocks functions that are called from the cpufreq driver on resume. Signed-off-by:
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Heiko Stuebner authored
This driver can handle the clock controllers of the socs mentioned above, as they share a common clock tree with only small differences. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As pll-rate-tables only the 12mhz variants are currently included. The original code was wrongly checking for 169mhz xti values [a 0 to much at the end], so the original 16mhz pll table would have never been included and its values are so obscure that I have no possibility to at least check their sane-ness. When using the formula from the manual the resulting frequency is near the table value but still slightly off. Signed-off-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Heiko Stuebner authored
Describe the clock controller of s3c2410, s3c2440 and s3c2442. Signed-off-by:
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Heiko Stuebner authored
Add platform device and select the correct implementation automatically depending on wether the old samsung_clock or the common clock framework is enabled. This is only done for machines already using the old dclk implementation, as everybody else should move to use dt anyway. The machine-specific settings for the external clocks will have to be set by somebody with knowledge about the specific hardware. Signed-off-by:
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- May 09, 2014
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Heiko Stuebner authored
This adds a driver for controlling the external clock outputs of s3c24xx architectures including the dclk muxes and dividers. The driver at the moment only supports the legacy non-dt boards using these clock outputs. The clock-output control itself is part of the system-controller mainly controlled by the pinctrl drivers. So it should most likely be integrated there for dt platforms. Signed-off-by:
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Heiko Stuebner authored
The s3c24xx cpufreq driver needs to change the mpll speed and was doing this by writing raw values from a translation table into the MPLLCON register. Change this to use a regular clk_set_rate call when using the common clock framework and only write the raw value in the samsung_clock case. The s3c cpufreq driver does already aquire the mpll, so simply add a reference to struct s3c_cpufreq_config to let set_fvco access it. While struct clk is opaque the differenciation between samsung clock and common clock is kept, as the samsung-clock mpll clk does not implement a real set_rate. Signed-off-by:
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- Apr 15, 2014
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Heiko Stuebner authored
Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Signed-off-by:
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Heiko Stuebner authored
This driver can handle the clock controller in the s3c2412 soc. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. Signed-off-by:
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Heiko Stuebner authored
Describe the clock controller of the s3c2412. Signed-off-by:
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Heiko Stuebner authored
The manuals do not give them explicit names like in later socs, so more generic names with a s3c2410-prefix were used for them. As it was common to do so in the previous implementation, functionality to change the pll rate is already included. Signed-off-by:
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Heiko Stuebner authored
The Samsung ccf driver already handles the save and restore of the clock registers on suspend and resume. The architecture code should not duplicate this when the ccf is active. Signed-off-by:
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Heiko Stuebner authored
This converts the mentioned platforms to use the newly introduced driver for the common clock framework for them. With this the whole legacy clock structure can go away too. Signed-off-by:
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Heiko Stuebner authored
This adds the clock controller itself, the xti clock on the smdk2416 as well as the clock references in the individual device nodes. Signed-off-by:
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Heiko Stuebner authored
As the conversion to the common-clock-framework is done in multiple steps, it is necessary to prevent conflicts between the different struct clk implementations. For this include the s3c24xx_setup_clocks function only when SAMSUNG_CLOCK is selected and make the socs we don't convert this time explicitly depend on SAMSUNG_CLOCK, which gets only selected automatically if COMMON_CLK is not enabled. Signed-off-by:
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Heiko Stuebner authored
The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by:
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Heiko Stuebner authored
Starting with the s3c2443 the s3c24xx series got a new clock tree compared to the previous s3c24xx socs. This binding describes the clock controller found in the s3c2443, s3c2416 and s3c2450 socs. Signed-off-by:
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