- Aug 21, 2023
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Rob Herring authored
The Aspeed pinctrl bindings are missing an additionalProperties/ unevaluatedProperties schemas on the child pin mux nodes which means any undefined properties are allowed. In addition, using 'additionalProperties' for child nodes with any name works better than a pattern matching everything with an if/then schema to select nodes only. With 'additionalProperties' added, 'pins' and 'bias-disable' properties need to be added as they were not defined. A $ref to pinmux-node.yaml which defines the common property types was also missing. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230819010907.916061-1-robh@kernel.org Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Rob Herring authored
'phandle' properties are implicitly supported on all nodes, so it shouldn't be listed in schemas. dtschema had a bug where 'phandle' and other implicit properties weren't being added under 'additionalProperties' schemas. That was fixed in v2023.07 release. Signed-off-by:
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- Aug 15, 2023
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Linus Walleij authored
Merge tag 'qcom-pinctrl-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel Qualcomm pinctrl changes for v6.6 1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio SubSystem) TLMM pin controllers. 2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin controllers. Signed-off-by:
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Neil Armstrong authored
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 gpio bindings. Acked-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Daniel Golle <daniel@makrotopia.org> Acked-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-3-04a0c5cdda52@linaro.org Signed-off-by:
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Neil Armstrong authored
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 pinctrl bindings. Acked-by:
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Neil Armstrong authored
Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 pinctrl & gpio. Acked-by:
Andy Shevchenko <andy@kernel.org> Signed-off-by:
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Stanislav Jakubek authored
Convert Broadcom BCM281xx pin controller bindings to DT schema. Signed-off-by:
Stanislav Jakubek <stano.jakubek@gmail.com> Reviewed-by:
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- Aug 10, 2023
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Florian Fainelli authored
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by:
Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by:
Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230808180733.2081353-3-florian.fainelli@broadcom.com Signed-off-by:
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Florian Fainelli authored
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us produce the "unable to add GPIO chip" message which is confusing. Use dev_err_probe() to silence probe deferral messages. Signed-off-by:
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Tony Lindgren authored
Use the "ti,am654-padconf" compatible to enable the use of wake-up enable and event bits on K3 SOCs that support the daisychain feature Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Dhruva Gole authored
Add the "ti,am654-padconf" compatible to support the new wakeup enable and status bits positions on K3 family SOCs that support the IO daisychain feature. Signed-off-by:
Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230808102207.130177-2-d-gole@ti.com Signed-off-by:
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Valentin Caron authored
Add stm32_pctrl_get_desc_pin_from_gpio function to find a stm32 pin descriptor which is matching with a gpio. Most of the time pin number is equal to pin index in array. So the first part of the function is useful to speed up. And during gpio bank register, we set default gpio names with pin names. Signed-off-by:
Valentin Caron <valentin.caron@foss.st.com> Acked-by:
Alexandre TORGUE <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20230620104349.834687-1-valentin.caron@foss.st.com Signed-off-by:
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Ruan Jinjie authored
Since commit ce753ad1 ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk"), there is no possible for platform_get_irq() to return 0. Use the return value from platform_get_irq(). Signed-off-by:
Ruan Jinjie <ruanjinjie@huawei.com> Link: https://lore.kernel.org/r/20230803094304.733371-1-ruanjinjie@huawei.com Signed-off-by:
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Sergey Shtylyov authored
In atmel_conf_pin_config_dbg_show(), checking atmel_pioctrl->pins[pin_id] against being NULL doesn't make any sense as it gets derefenced first and the driver's probe() method immediately returns -ENOMEM when devm_kzalloc() returns NULL for any atmel_pioctrl->pins[] element anyway, thus failing to register the device... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by:
Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/4ab2f59f-45c1-76a2-94da-3331e8ec4e35@omp.ru Signed-off-by:
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Krzysztof Kozlowski authored
The recommended name for enable GPIOs property in regulator-gpio is "enable-gpios". This is also required by bindings: ste-hrefv60plus-stuib.dtb: regulator-gpio: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Signed-off-by: -
Claudiu Beznea authored
devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 0f04a817 ("pinctrl: mcp23s08: Split to three parts: core, I²C, SPI") Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230621100409.1608395-1-claudiu.beznea@microchip.com Signed-off-by:
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- Aug 07, 2023
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Huqiang Qin authored
Replacing IRQ numbers with IRQID macro definitions makes node properties easier to understand and also makes GPIO interrupts easier to use. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by:
Huqiang Qin <huqiang.qin@amlogic.com> Reviewed-by:
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Huqiang Qin authored
Replacing IRQ numbers with IRQID macro definitions makes driver code easier to understand. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by:
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Huqiang Qin authored
Add a new dt-binding header that details the interrupt number of the GPIO. Signed-off-by:
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Tony Lindgren authored
Update binding for yaml and remove the old related txt bindings. Note that we are also adding the undocumented pinctrl-single,slew-rate property. And we only use the first example from the old binding. As we are mostly using a generic compatible across various SoCs, let's not start adding matches for random pin group node naming. Let's standardize on pin group node name ending in -pins with an optional instance number suffix. As a pin group may have additional pins added to it later on, let's always use -pins rather than -pin for the gropu name. Most of the dts files have been updated already for the pin group node names with a few changes still pending. Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
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Sricharan Ramabadhran authored
When building with clang toolchain and arm64-randconfig-r015-20230712 kernel test robot reports the below warning. drivers/pinctrl/qcom/pinctrl-ipq5018.c:244:27: warning: unused variable '_groups' [-Wunused-const-variable] static const char * const _groups[] = { ^ 1 warning generated. static const char * const _groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", }; Fixing it by removing the variable. Reported-by:kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307120814.vWPY6URk-lkp@intel.com/ Fixes: 725d1c89 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Signed-off-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Reviewed-by:
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Konrad Dybcio authored
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org Signed-off-by:
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Konrad Dybcio authored
Add bindings for pin controller in SM6115 Low Power Audio SubSystem LPASS). Signed-off-by:
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Sai Krishna Potthuri authored
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. Using these pinctrl properties observed hang issues with older PMUFW(Xilinx ZynqMP Platform Management Firmware), hence reverted the patch. Commit 9989bc33 ("Revert "pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance""). Support for configuring these properties added in PMUFW Configuration Set version 2.0. When there is a request for these configurations from pinctrl driver for ZynqMP platform, xilinx firmware driver checks for this version before configuring these properties to avoid the hang issue and proceeds further only when firmware version is >=2 otherwise it returns error. Signed-off-by:
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Reviewed-by:
Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230731095026.3766675-5-sai.krishna.potthuri@amd.com Signed-off-by:
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Sai Krishna Potthuri authored
Add 'output-enable' configuration parameter to the properties list. Using these pinctrl properties observed hang issues with older Xilinx ZynqMP Platform Management Firmware, hence reverted the patch previously. Commit ff835606 ("Revert "dt-bindings: pinctrl-zynqmp: Add output-enable configuration""). Support for configuring these properties added in Xilinx ZynqMP Platform Management firmware(PMUFW) Configuration Set version 2.0. Linux firmware driver checks if the configuration is supported by the PMUFW when it gets request for TRISTATE configuration from pinctrl driver. If it supports, then calls will be made otherwise it returns error. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230731095026.3766675-4-sai.krishna.potthuri@amd.com Signed-off-by:
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Sai Krishna Potthuri authored
Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx ZynqMP Platform Management Firmware) Configuration Param Set version 2.0. If the requested configuration is TRISTATE and platform is ZYNQMP then check the version before requesting Xilinx firmware to set the configuration. Signed-off-by:
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Dhaval Shah authored
Add function to get family code and sub family code from the idcode. This family code and sub family code helps to identify the platform. Family code of any platform is on bits 21 to 27 and Sub family code is on bits 19 and 20. Signed-off-by:
Dhaval Shah <dhaval.r.shah@amd.com> Signed-off-by:
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- Aug 03, 2023
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.6 - Use the new devm_clk_get_enabled() helper. Signed-off-by:
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- Jul 29, 2023
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Sergey Shtylyov authored
pinctrl_generic_add_function() doesn't check result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by:
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Sergey Shtylyov authored
pinctrl_register_one_pin() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by:
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Sergey Shtylyov authored
pinctrl_generic_add_group() doesn't check the result of radix_tree_insert() despite they both may return a negative error code. Linus Walleij said he has copied the radix tree code from kernel/irq/ where the functions calling radix_tree_insert() are *void* themselves; I think it makes more sense to propagate the errors from radix_tree_insert() upstream if we can do that... Found by Linux Verification Center (linuxtesting.org) with the Svace static analysis tool. Signed-off-by:
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- Jul 26, 2023
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Krzysztof Kozlowski authored
Document qcom,pmc8180-gpio and qcom,pmc8180c-gpio compatibles already used in DTS and in the same binding in allOf:if:then section for narrowing available GPIOs: sc8180x-primus.dtb: pmic@4: gpio@c000:compatible:0: 'qcom,pmc8180c-gpio' is not one of ... Fixes: 04bed640 ("dt-bindings: pinctrl: qcom,pmic-gpio: describe gpio-line-names") Acked-by:
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Konrad Dybcio authored
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by:
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Konrad Dybcio authored
Add bindings for pin controller in SM6115 Low Power Audio SubSystem LPASS). Signed-off-by:
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- Jul 25, 2023
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Christophe JAILLET authored
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). While at it, use dev_err_probe() which filters -EPROBE_DEFER. Signed-off-by:Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr [geert: Make clk local to rzg2l_pinctrl_probe()] Signed-off-by:
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Geert Uytterhoeven authored
Simplify clock handling by using the devm_clk_get_enabled() helper, instead of open-coding the same operations. Move the clock pointer from the driver-private data to a local variable, as it is not needed outside the .probe() callback. Signed-off-by:
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Krzysztof Kozlowski authored
Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org Signed-off-by:
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Krzysztof Kozlowski authored
Add bindings for pin controller in SM8350 Low Power Audio SubSystem (LPASS). Reviewed-by:
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- Jul 24, 2023
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Mario Limonciello authored
On some systems amd_pinconf_set() is called with parameters 0x8 (PIN_CONFIG_DRIVE_PUSH_PULL) or 0x14 (PIN_CONFIG_PERSIST_STATE) which are not supported by pinctrl-amd. Don't show an err message when called with an invalid parameter, downgrade this to debug instead. Cc: stable@vger.kernel.org # 6.1 Fixes: 635a750d ("pinctrl: amd: Use amd_pinconf_set() for all config options") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20230717201652.17168-1-mario.limonciello@amd.com Signed-off-by:
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Huqiang Qin authored
Add a new pinctrl driver for Amlogic C3 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by:
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