- Sep 02, 2016
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
Gabriel Krisman Bertazi <krisman@linux.vnet.ibm.com> Signed-off-by:
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
Tobias Klauser <tklauser@distanz.ch> Signed-off-by:
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Signed-off-by:
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Julia Lawall authored
Check for uart_ops structures that are only stored in the ops field of a uart_port structure. This field is declared const, so uart_ops structures that have this property can be declared as const also. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct uart_ops i@p = { ... }; @ok@ identifier r.i; struct uart_port e; position p; @@ e.ops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct uart_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct uart_ops i = { ... }; // </smpl> Signed-off-by:
Vineet Gupta <vgupta@synopsys.com> Signed-off-by:
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Kefeng Wang authored
Use an unified new dev variable instead of &pdev->dev and p->dev in probe function. Reviewed-by:
Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by:
Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by:
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- Aug 31, 2016
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Nandor Han authored
Update error counters when DMA is used for receiving data. Do this by using DMA transaction error event instead error interrupts to reduce interrupt load. Tested-by:
Peter Senna Tschudin <peter.senna@collabora.com> Acked-by:
Nandor Han <nandor.han@ge.com> Signed-off-by:
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Nandor Han authored
The IMX UART has a 32 bytes HW buffer which can be filled up in 2777us at 115200 baud or 80us at 4Mbaud (supported by IMX53). Taking this in consideration there is a good probability to lose data because of the DMA startup latency. Our tests (explained below) indicates a latency up to 4400us when creating interrupt load and ~70us without. When creating interrupt load I was able to see continuous overrun errors by checking serial driver statistics using the command: `cat /proc/tty/driver/IMX-uart`. Replace manual restart of DMA with cyclic DMA to eliminate data loss due to DMA engine startup latency (similar approch to atmel_serial.c driver). As result the DMA engine will start on the first serial data transfer and stops only when serial port is closed. Tests environment: Using the m53evk board I have used a GPIO for profiling the IMX serial driver. - The RX line and GPIO were connected to oscilloscope. - Run a small test program on the m53evk board that will only open and read data from ttymxc2 port. - Connect the ttymxc2 port to my laptop using a USB serial converter where another test program is running, able to send configurable packet lengths and intervals. - Serial ports configured at 115200 8N1. - Interrupts load created by disconnecting/connecting (3s interval) a USB hub, using a digital switch, with 4 USB devices (USB-Serial converter, USB SD card, etc) connected. (around 160 interrupts/second generated) - The GPIO was toggled HI in the `imx_int` when USR1_RRDY or USR1_AGTIM events are received and toggled back, once the DMA configuration is finalized, at the end of `imx_dma_rxint`. Measurements: The measurements were done from the end of the last byte (RX line) until the GPIO was toggled back LOW. Note: The GPIO toggling was done using `gpiod_set_value` method. Tests performed: 1. Sending 9 bytes packets at 8ms interval. Having the 9 bytes packets will activate the RRDY threshold event and IMX serial interrupt called. Results: - DMA start latency (interrupt start latency + DMA configuration) consistently 70us when system not loaded. - DMA start latency up to 4400us when system loaded. 2. Sending 40 bytes packet at 8mS interval. Results with load: - Able to observe overruns by running: `watch -n1 cat /proc/tty/driver/IMX-uart` Tested-by: -
Nandor Han authored
The calculation of the DMA transaction residue supports only fixed size data transfers. This implementation is not covering all operations (e.g. data receiving) when we need to know the exact amount of bytes transferred. The loop channels handling was changed to clear the buffer descriptor errors and use the bd->mode.count to calculate the residue. Tested-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
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Nandor Han authored
Having the SDMA driver use a tasklet for running the clients callback introduce some issues: - probability to have desynchronized data because of the race condition created since the DMA transaction status is retrieved only when the callback is executed, leaving plenty of time for transaction status to get altered. - inter-transfer latency which can leave channels idle. Move the callback execution, for cyclic channels, to SDMA interrupt (as advised in `Documentation/dmaengine/provider.txt`) to (a)reduce the inter-transfer latency and (b) eliminate the race condition possibility where DMA transaction status might be changed by the time is read. The responsibility of the SDMA interrupt latency is moved to the SDMA clients which case by case should defer the work to bottom-halves when needed. Tested-by: -
Andy Shevchenko authored
DMA on Intel Quark SoC is a part of UART IP block. Enable it. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by:
Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by:
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Andy Shevchenko authored
Intel Quark SoC supports MSI for LPSS, in particular for UART. Enable MSI for Intel Quark. Signed-off-by:
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Andy Shevchenko authored
Intel Quark has DesignWare UART. Move the code from 8250_pci to 8250_lpss. Reviewed-by:
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Andy Shevchenko authored
The SoCs, such as Intel Braswell, have DesignWare UART IP. Split out the support of such chips to a separate module which also will be used for Intel Quark later. The rationale to have the separate driver to be existing: - Do not contaminate 8250_pci.c anymore with LPSS related quirks - All of them are using same DMA engine and they are Designware IP which means that in the future we might share the code between 8250_dw.c and 8250_lpss.c - It reduces the kernel memory footprint on non-X86 machines where 8250_pci.c is in use Besides the split the driver also has been refactored, in particular a) the DMA and port setup are separate functions, b) the two new structures lpss8250 and lpss8250_board are introduced to keep necessary data instead of pciserial_board, c) DMA parameters are passed to the DMA setup via mentioned custom structure. Most of the changes are done due to the future support of UART DMA on Intel Quark. The Intel Quark UART DMA support is based on bits taking from BSP code published by Intel earlier. The driver does not use any specific power management. PCI core takes care of the default behaviour during suspend and resume. Signed-off-by:
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Andy Shevchenko authored
Intel Quark has 16550A compatible UART with autoflow feature enabled. It has only 16 bytes of FIFO. Currently serial8250_do_set_termios() prevents to enable autoflow since the minimum requirement of 32 bytes of FIFO size. Drop a FIFO size limitation to allow autoflow control be enabled on such UARTs. While here, comment out UART_CAP_AFE for PORT_AR7 since it wasn't working and it will be not a good idea to use it in conjunction with trigger level of 1 byte. Suggested-by:
Peter Hurley <peter@hurleysoftware.com> Reviewed-by:
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Andy Shevchenko authored
Some UARTs, e.g. one is used in Intel Quark, have a different address base for DMA operations. Introduce an additional field (per RX and TX DMA channels) in struct uart_8250_dma to cover those cases. Reviewed-by:
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Andy Shevchenko authored
Convert dmaengine_terminate_all() calls to synchronous and asynchronous versions where appropriate. Reviewed-by:
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Andy Shevchenko authored
Some users consider DMA optional, thus when driver is not compiled we shouldn't prevent compilation of the users. Add stubs for dw_dma_probe() and dw_dma_remove(). Acked-by:
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Andy Shevchenko authored
There are at least two known devices, e.g. DMA controller found on ARC AXS101 SDP board, that have LLP register and no multi block transfer support at the same time. Override autodetection by user provided data. Reported-by:
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by:
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Andy Shevchenko authored
Intel Quark UART uses DesignWare DMA IP. Though the DMA IP is connected in such way that handshake interface uses inverted polarity. We have to provide a possibility to set this in the DMA driver when configuring a channel. Introduce a new member of custom slave configuration called 'hs_polarity' and set active low polarity in case this value is 'true'. Acked-by:
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Andy Shevchenko authored
It seems we need to extend custom slave configuration by one more member to support Intel Quart UART. It becomes a burden to manage all members of struct dw_dma_slave one-by-one. Replace the set of fields by embedding struct dw_dma_slave into struct dw_dma_chan. Acked-by:
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Florian Vallee authored
Previously sc16is7xx_power was called in order to set the device to a low power mode. However since SC16IS7XX_EFR_ENABLE_BIT was not set beforehand this suspend request had not effect. Also, soft-reset the device prior to port initialization. It may otherwise be in a state (interrupt pending, fifo not empty) which prevents it from sleeping. Signed-off-by:
Florian Vallee <fvallee@eukrea.fr> Signed-off-by:
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Eddie Huang authored
mediatek can support baud rate up to 4M. the 'uart_get_baud_rate' function will limit the max baud rate. Modify max baud to remove the limit. Signed-off-by:
Long Cheng <long.cheng@mediatek.com> Signed-off-by:
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Julia Lawall authored
Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/ ) // <smpl> @@ expression e1,e2; statement S2,S1; @@ - if (of_get_property(e1,e2,NULL)) + if (of_property_read_bool(e1,e2)) S1 else S2 // </smpl> Signed-off-by:
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Bhuvanchandra DV authored
Enable Vybrid's build-in support for RS-485 auto RTS for controlling line direction of RS-485 transceiver driver. Enable RS485 feature by either using ioctrl 'TIOCSRS485' or enable it in the device tree by setting 'linux,rs485-enabled-at-boot-time' property. Signed-off-by:
Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by:
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Bhuvanchandra DV authored
When DMA mode is enabled one need to make sure the DMA channels are idle before entering suspend mode especially when UART ports which are set as wakeup source and console port with no_console_suspend is set. This patch takes care of gracefully releasing DMA channels for the above two cases and start the DMA at resume. Signed-off-by:
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Bhuvanchandra DV authored
Drop PIO to DMA switching and use scatter/gather DMA for Tx path to improve performance. Some part of the code is borrowed from imx serial driver. Signed-off-by:
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Bhuvanchandra DV authored
The initial approach of DMA implementatin for RX is inefficient due to switching from PIO to DMA, this leads to overruns especially on instances with the smaller FIFO. To address these issues this patch uses a cyclic DMA for receiver path. Some part of the code is borrowed from atmel serial driver. Signed-off-by:
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Bhuvanchandra DV authored
By default the driver always configure the mode as 8s1 even when 8m1 mode is selected. Fix this by adding support to control the space/mark bit. Signed-off-by:
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Stefan Agner authored
Commit 8e4934c6 ("tty: serial: fsl_lpuart: clear receive flag on FIFO flush") implemented clearing of the receive flag by reading the status register only. It turned out that even though we flush the FIFO afterwards, a explicit read of the data register is still required. This leads to a FIFO underrun. To avoid this, follow the advice in the overrun "Operation section": Unconditionally clear RXUF after using RXFLUSH. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Stefan Agner authored
Add suspend/resume support. Signed-off-by:
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Stefan Agner authored
Currently the tx_empty callback only considers the Transmit Complete Flag (TC). The reference manual is not quite clear if the TC flag covers the TX FIFO too. Debug prints on real hardware have shown that from time to time the TC flag is asserted (indicating Transmitter idle) while there are still data in the TX FIFO. Hence, in this case the serial core will call the shutdown callback even though there are data remaining in the TX FIFO buffers. Avoid early shutdowns by considering the TX FIFO empty flag too. Also avoid theoretical race conditions between DMA and the driver by checking whether the TX DMA is in progress too. Signed-off-by:
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Kefeng Wang authored
It should check the data->pclk, not data->clk when get apb_pclk. Fixes: c8ed99d4 ("serial: 8250_dw: Add support for deferred probing") Signed-off-by:
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Christophe JAILLET authored
The 2nd parameter of 'find_first_zero_bit' is the number of bits to search. In this case, we are passing 'sizeof(vt8500_ports_in_use)'. 'vt8500_ports_in_use' is an 'unsigned long'. So the sizeof is likely to return 4 on a 32 bits kernel. A few lines below, we check if it is below VT8500_MAX_PORTS, which is 6. It is likely that the number of bits in a long was expected here. In order to fix it: - use DECLARE_BITMAP when declaring the vt8500_ports_in_use - use VT8500_MAX_PORTS as a maximum value when checking/setting bits in this bitmap - modify code now that 'vt8500_ports_in_use' has become a pointer because of the use of DECLARE_BITMAP It has been spotted by the following coccinelle script: @@ expression ret, x; @@ * ret = \(find_first_bit \| find_first_zero_bit\) (x, sizeof(...)); Signed-off-by:Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Rob Herring authored
tty_port_close handles much of the common parts of tty close. Convert uart_close to use it and move the serial_core specific parts into tty_port.shutdown function. This will be needed to use tty_port functions directly from in kernel clients. This change causes ops->stop_rx() to be called after uart_wait_until_sent() is called which I think should be fine. Otherwise, the sequence of the close should be the same. Cc: Peter Hurley <peter@hurleysoftware.com> Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
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Rob Herring authored
tty_port_open handles much of the common parts of tty opening. Convert uart_open to use it and move the serial_core specific parts into tty_port.activate function. This will be needed to use tty_port functions directly from in kernel clients. The tricky part is uart_port_startup can return positive values to allow setserial to configure the port. We now return the positive value to tty_port_open so that the tty is not marked as initialized and then set the return value in uart_open to 0. Cc: Peter Hurley <peter@hurleysoftware.com> Signed-off-by:
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Krzysztof Kozlowski authored
The Samsung serial driver registered for CPU frequency transitions to recalculate its clock when ARM clock frequency changes. This is needed only on S3C24xx platform so limit the ifdef to respective cpufreq driver. On S3C24xx the ratio ratio between frequencies of UART's parent clock (pclk) and ARM's parent clock (fclk) remains fixed. Therefore when ARM clock frequency goes down, the serial is also affected. Suggested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
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