- Jul 23, 2014
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Daniel Vetter authored
We only need to check for this in psr_enable, everything else is already protect by the dev_priv->psr.enabled checks. Those need the psr locking, but these functions are called infrequent enough that the locking overhead is negligible. Suggested by Chris Wilson. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Add busy_frontbuffer_bits and locking. Reviewed-by:
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Daniel Vetter authored
I've tried to split this up, but all the changes are so tightly related that I didn't find a good way to do this without breaking bisecting. Essentially this completely changes how psr is glued into the overall driver, and there's not much you can do to soften such a paradigm change. - Use frontbuffer tracking bits stuff to separate disable and re-enable. - Don't re-check everything in the psr work. We have now accurate tracking for everything, so no need to check for sprites or tiling really. Allows us to ditch tons of locks. - That in turn allows us to properly cancel the work in the disable function - no more deadlocks. - Add a check for HSW sprites and force a flush. Apparently the hardware doesn't forward the flushing when updating the sprite base address. We can do the same trick everywhere else we have such issues, e.g. on baytrail with ... everything. - Don't re-enable psr with a delay in psr_exit. It really must be turned off forever if we detect a gtt write. At least with the current frontbuffer render tracking. Userspace can do a busy ioctl call or no-op pageflip to re-enable psr. - Drop redundant checks for crtc and crtc->active - now that they're only called from enable this is guaranteed. - Fix up the hsw port check. eDP can also happen on port D, but the issue is exactly that it doesn't work there. So an || check is wrong. - We still schedule the psr work with a delay. The frontbuffer flushing interface mandates that we upload the next full frame, so need to wait a bit. Once we have single-shot frame uploads we can do better here. v2: Don't enable psr initially, rely upon the fb flush of the initial plane setup for that. Gives us more unified code flow and makes the crtc enable sequence less a special case. v3: s/psr_exit/psr_invalidate/ for consistency v4: Fixup whitespace. v5: Correctly bail out of psr_invalidate/flush when dev_priv->psr.enabled is NULL. Spotted by Rodrigo. v6: - Only schedule work when there's work to do. Fixes WARNINGs reported by Rodrigo. - Comments Chris requested to clarify the code. v7: Fix conflict on rebase (Rodrigo) Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Daniel Vetter authored
It's not really optional to have locking ... The ugly part is how much locking the psr work needs since it has to recheck everything. Which is way too much. But we need to ditch the psr work in it's current form anyway and implement proper frontbuffer tracking. The other nasty bit that had to go was the delayed work cancle in psr_exit. Which means a bunch of races just became a bit more likely, but mea culpa. v2: Fixup HAS_PSR checks, resulting in uninitialized mutex issues. Reviewed-by:
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Daniel Vetter authored
We need to make sure that no one else is using this in the enable function and also that the work item hasn't raced with the disabled function. v2: Improve bisectability by moving one hunk to an earlier patch. v3: added missing dev_priv declaration (Rodrigo) Reviewed-by:
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Daniel Vetter authored
Make sure we track the sw side (psr.active) correctly and WARN everywhere it might get out of sync with the hw. v2: Fixup WARN_ON logic inversion, reported by Rodrigo. Reviewed-by:
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Daniel Vetter authored
It's disabled already except when we've raced. Reviewed-by:
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Daniel Vetter authored
Trying to fish that one out through looping is a bit a locking nightmare. So just set it and use it in the work struct. v2: - Don't Oops in psr_work, spotted by Rodrigo. - Fix compile warning. Reviewed-by:
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Daniel Vetter authored
Can't review this right now due to lack of DRRS code. Reviewed-by:
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Daniel Vetter authored
Due to runtime pm and system s/r we need to restore hw state every time we enable a pipe again. Hence trying to avoid that is just pointless book-keeping which Rodrigo then tried to work around by manually adding psr_setup calls to our resume code. Much simpler to just remove code instead. v2: Properly bail out of psr exit if psr isn't enabled. Spotted by Rodrigo. Reviewed-by:
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Borun Fu authored
On VLV, after i915_pm_suspend display power wells are staying power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" Display is staing D0 State. There might be better way/place to power gate these wells. Also, we need to make sure that if wells are power gated due to DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. [Daniel] Cc: Imre Deak <imre.deak@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 Signed-off-by:
Borun Fu <borun.fu@intel.com> Signed-off-by:
Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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- Jul 12, 2014
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Fengguang Wu authored
CC: Deepak S <deepak.s@linux.intel.com> CC: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Mika Kuoppala authored
The register to read cz count is different from vlv. Also the counts returned from CCK_CTL1 for BSW are (ticks in 30ns - 1). czcount_30ns of value 1 is a special case for 320Mhz. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80703 Suggested-by:
Deepak S <deepak.s@linux.intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Tested-by:
Guo Jinxian <jinxianx.guo@intel.com> Reviewed-by:
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Sagar Kamble authored
Cc: damien.lespiau@intel.com Cc: daniel.vetter@ffwll.ch Cc: ville.syrjala@linux.intel.com Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Acked-by:
Dave Airlie <airlied@linux.ie> Signed-off-by:
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Sagar Kamble authored
These property descriptions were kept as placeholder. Removing them for simplicity. Cc: damien.lespiau@intel.com Cc: daniel.vetter@ffwll.ch Cc: ville.syrjala@linux.intel.com Signed-off-by:
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Ville Syrjälä authored
drm_rotation_simplify() can be used to eliminate unsupported rotation flags. It will check if any unsupported flags are present, and if so it will modify the rotation to an alternate form by adding 180 degrees to rotation angle, and flipping the reflect x and y bits. The hope is that this identity transform will eliminate the unsupported flags. Of course that might not result in any more supported rotation, so the caller is still responsible for checking the result afterwards. Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Acked-by:
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Ville Syrjälä authored
Add some helper functions to move drm_rects between different rotated coordinate spaces. One function does the forward transform and another does the inverse. Cc: dri-devel@lists.freedesktop.org Signed-off-by:
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Ville Syrjälä authored
Use the new drm_mode_create_rotation_property() in omapdrm. Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Rob Clark <robdclark@gmail.com> Reviewed-by:
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Ville Syrjälä authored
Add a function to create a standards compliant rotation property. Signed-off-by:
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Ville Syrjälä authored
Make drm_property_create_bitmask() a bit more generic by allowing the caller to specify which bits are in fact supported. This allows multiple callers to use the same enum list, but still create different versions of the same property with different list of supported bits. v2: Populate values[] array as non-sparse Make supported_bits 64bit Fix up omapdrm call site (Rob) Cc: dri-devel@lists.freedesktop.org Signed-off-by: -
Ville Syrjälä authored
The rotation property stuff should be standardized among all drivers. Move the bits to drm_crtc.h from omap_drv.h. Signed-off-by:
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Deepak S authored
This is useful for userspace utilities to verify and micromanaging the increase/decrease frequncy. v2: Use vlv_gpu_freq to get freq (Deepak) Signed-off-by:
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Deepak S authored
Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same for CHV. Signed-off-by:
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Deepak S authored
Adding chv specific fre/encode conversion. v2: Remove generic function and platform check (Daniel) Signed-off-by:
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Deepak S authored
We need mem_freq or cz clock for freq/opcode conversion Signed-off-by:
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Deepak S authored
This is useful for userspace utilities to verify and micromanaging the increase/decrease frequncy. Signed-off-by:
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Deepak S authored
Reading RP1 for valleyview to help us enable "pm_rps" i-g-t testcase execution. Signed-off-by:
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Ville Syrjälä authored
VLV and CHV disable the DP port only in the .post_disable() hook, so we need to make intel_sanitize_encoder() call that when it's trying to disable encoders without an active pipes. My bsw actaully hits this when an external display is connected. The BIOS still likes to turn on the eDP port, but leaves the pipe disabled. Signed-off-by:
Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by:
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Daniel Vetter authored
Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Remove now bogus comment.] Signed-off-by:
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- Jul 11, 2014
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Ville Syrjälä authored
No need to re-read the hardware rps fuses when we already have all the values tucked away in dev_priv->rps. Signed-off-by:
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Ville Syrjälä authored
In commit 62942ed7 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Jun 13 09:28:33 2014 -0700 drm/i915/vlv: disable PPGTT on early revs v3 we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to explicitly avoid disabling PPGTT on CHV. Signed-off-by:
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Chris Wilson authored
We can eliminate a lot of special case code by making the computation of the interrupt mask be correct for all callers. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
Place the RPS counters inside the RPS struct. Signed-off-by:
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Damien Lespiau authored
C is super happy to asign anything pointer to void *. Don't pretend otherwise. Signed-off-by:
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Paulo Zanoni authored
We may reach this point while the machine is still runtime suspended, so we'll hit a WARN. The other encoders also don't touch registers at this point, so instead of waking the machine up, write some code to keep the register always at the same state, including after we runtime suspend/resume. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by:
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Paulo Zanoni authored
Just like we do for the other encoders. This should fix some WARNs when running pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by:
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Paulo Zanoni authored
Just like we already do in haswell_get_pipe_config(). This should prevent some WARNs when we run pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by:
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Paulo Zanoni authored
Since we now have support for shared DPLLS. Signed-off-by:
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Daniel Vetter authored
To be able to do this we need to separately keep track of how many crtcs need a given WRPLL and how many actually actively use it. The common shared dpll framework already has all this, including massive state readout and cross checking. Which allows us to do this switch in a fairly small patch. Reviewed-by:
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Daniel Vetter authored
Mostly this patch is one big excersize in deleting code and asserts which are no longer needed. Note that we still abuse the shared dpll framework a bit since we call the enable/disable functions from the crtc mode_set and off hooks. But changing the actual hardware sequence will be done in the next step. Note that besides the massive amount of changes in this patch the places and order in which the low-level WRPLL code is called is absolutely unchanged. Signed-off-by:
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