- Exit pcitest with error code when test fails (Jean-Jacques Hiblot)

  - Fix leaked of_node references in dra7xx, uniphier, layerscape,
    rockchip, aardvark, iproc, mediatek, rpadlpar (Wen Yang)

  - Fix pcitest "help" option parsing (Kishon Vijay Abraham I)

  - Fix Makefile bug that inadvertently removes pcitest.sh (Kishon Vijay
    Abraham I)

  - Check for alloc_workqueue() failure in endpoint test driver (Kangjie
    Lu)

* remotes/lorenzo/pci/misc:
  PCI: endpoint: Fix a potential NULL pointer dereference
  tools: PCI: Handle pcitest.sh independently from pcitest
  tools: PCI: Add 'h' in optstring of getopt()
  PCI: mediatek: Fix a leaked reference by adding missing of_node_put()
  PCI: iproc: Fix a leaked reference by adding missing of_node_put()
  PCI: aardvark: Fix a leaked reference by adding missing of_node_put()
  PCI: rockchip: Fix a leaked reference by adding missing of_node_put()
  PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put()
  PCI: uniphier: Fix a leaked reference by adding missing of_node_put()
  PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put()
  tools: PCI: Exit with error code when test fails

  - Check for __get_free_pages() failure in xilinx (Kangjie Lu)

* remotes/lorenzo/pci/xilinx:
  PCI: xilinx: Check for __get_free_pages() failure

  - Use DMA-API to get tegra MSI address to prevent device DMA from
    generating unwanted MSIs (Vidya Sagar)

* remotes/lorenzo/pci/tegra:
  PCI: tegra: Use the DMA-API to get the MSI address

  - Fix rockchip bitwise operations that overflow type (Colin Ian King)

* remotes/lorenzo/pci/rockchip:
  PCI: rockchip: Fix rockchip_pcie_ep_assert_intx() bitwise operations

  - Use BIT() when appropriate in rcar (Marek Vasut)

  - Use u32 to match rcar hardware register widths (Marek Vasut)

  - Use BITS_PER_BYTE when appropriate in rcar (Marek Vasut)

  - Remove unnecessary casts in rcar (Marek Vasut)

  - Fix 64-bit MSI target addresses in rcar (Marek Vasut)

  - Check for __get_free_pages() failure in rcar (Kangjie Lu)

  - Fix shadowed rcar "irq" variable (Wolfram Sang)

* remotes/lorenzo/pci/rcar:
  PCI: rcar: Do not shadow the 'irq' variable
  PCI: rcar: Fix a potential NULL pointer dereference
  PCI: rcar: Fix 64bit MSI message address handling
  PCI: rcar: Clean up debug messages
  PCI: rcar: Replace (8 * n) with (BITS_PER_BYTE * n)
  PCI: rcar: Replace various variable types with unsigned ones for register values
  PCI: rcar: Replace unsigned long with u32/unsigned int in register accessors
  PCI: rcar: Clean up remaining macros defining bits

# Conflicts:
#	drivers/pci/controller/pcie-rcar.c

  - Make mediatek clocks optional, not required (Chunfeng Yun)

  - Remove unused mediatek mt2712 "num-lanes" DT property (Honghui Zhang)

* remotes/lorenzo/pci/mediatek:
  arm64: dts: mt2712: Remove un-used property for PCIe
  PCI: mediatek: Get optional clocks with devm_clk_get_optional()

  - Move IRQ register address computation inside macros (Kishon Vijay
    Abraham I)

  - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I)

  - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham
    I)

  - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon
    Vijay Abraham I)

  - Add dwc support for platforms with custom MSI controllers (Kishon Vijay
    Abraham I)

  - Add keystone-specific MSI controller (Kishon Vijay Abraham I)

  - Remove dwc host_ops previously used for keystone-specific MSI (Kishon
    Vijay Abraham I)

  - Skip dwc default MSI init if platform has custom MSI controller (Kishon
    Vijay Abraham I)

  - Implement .start_link() and .stop_link() for keystone endpoint support
    (Kishon Vijay Abraham I)

  - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I)

  - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon
    Vijay Abraham I)

  - Get keystone register resources from DT by name, not index (Kishon
    Vijay Abraham I)

  - Get DT resources in .probe() to prepare for endpoint support (Kishon
    Vijay Abraham I)

  - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration
    (Kishon Vijay Abraham I)

  - Explicitly set keystone to host mode (Kishon Vijay Abraham I)

  - Document DT "atu" reg-names requirement for DesignWare core >= 4.80
    (Kishon Vijay Abraham I)

  - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon
    Vijay Abraham I)

  - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon
    Vijay Abraham I)

  - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham
    I)

  - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham
    I)

  - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I)

  - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I)

  - Make of_pci_get_max_link_speed() available to endpoint drivers as well
    as host drivers (Kishon Vijay Abraham I)

  - Add keystone support for DT "max-link-speed" property (Kishon Vijay
    Abraham I)

  - Add endpoint library support for BAR buffer alignment (Kishon Vijay
    Abraham I)

  - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I)

  - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay
    Abraham I)

  - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon
    Vijay Abraham I)

  - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay
    Abraham I)

  - Configure designware endpoints to advertise smallest resizable BAR
    (1MB) (Kishon Vijay Abraham I)

  - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay
    Abraham I)

  - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I)

  - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/keystone:
  misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
  misc: pci_endpoint_test: Add support to test PCI EP in AM654x
  PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
  PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
  PCI: keystone: Add support for PCIe EP in AM654x Platforms
  dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
  PCI: dwc: Add callbacks for accessing dbi2 address space
  PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
  PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
  PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
  PCI: keystone: Add support to set the max link speed from DT
  PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
  PCI: keystone: Invoke phy_reset() API before enabling PHY
  PCI: keystone: Add support for PCIe RC in AM654x Platforms
  dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
  PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
  PCI: dwc: Fix ATU identification for designware version >= 4.80
  PCI: dwc: Enable iATU unroll for endpoint too
  dt-bindings: PCI: Document "atu" reg-names
  PCI: keystone: Explicitly set the PCIe mode
  dt-bindings: PCI: Add dt-binding to configure PCIe mode
  PCI: keystone: Move resources initialization to prepare for EP support
  PCI: keystone: Use platform_get_resource_byname() to get memory resources
  PCI: keystone: Perform host initialization in a single function
  dt-bindings: PCI: keystone: Add "reg-names" binding information
  PCI: keystone: Cleanup error_irq configuration
  PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
  PCI: dwc: Remove default MSI initialization for platform specific MSI chips
  PCI: dwc: Remove Keystone specific dw_pcie_host_ops
  PCI: keystone: Use Keystone specific msi_irq_chip
  PCI: dwc: Add support to use non default msi_irq_chip
  PCI: keystone: Cleanup ks_pcie_msi_irq_handler()
  PCI: keystone: Use hwirq to get the MSI IRQ number offset
  PCI: keystone: Add separate functions for configuring MSI and legacy interrupt
  PCI: keystone: Cleanup interrupt related macros

# Conflicts:
#	drivers/pci/controller/dwc/pcie-designware.h

  - Work around iproc CRS completion issues (Srinath Mannam)

  - Allow smaller iproc outbound windows so driver can work on 32-bit
    systems (Srinath Mannam)

  - Use iproc-specific config read for PAXBv2 (not PAXB) (Srinath Mannam)

* remotes/lorenzo/pci/iproc:
  PCI: iproc: Enable iProc config read for PAXBv2
  PCI: iproc: Allow outbound configuration for 32-bit I/O region
  PCI: iproc: Add CRS check in config read

  - Simplify imx7d_pcie_wait_for_phy_pll_lock() by using
    regmap_read_poll_timeout() (Andrey Smirnov)

  - Drop imx6_pcie_wait_for_link() in favor of the more generic
    dw_pcie_wait_for_link() (Andrey Smirnov)

  - Return -ETIMEDOUT instead of -EINVAL from
    imx6_pcie_wait_for_speed_change() (Andrey Smirnov)

  - Remove unused PCIE_PL_PFLR_* constants from imx6 (Andrey Smirnov)

  - Use shared PHY debug register definitions in imx6 (Andrey Smirnov)

  - Use BIT() in imx6 (Andrey Smirnov)

  - Simplify imx6 PHY bit operations (Andrey Smirnov)

  - Simplify imx6 pcie_phy_poll_ack() (Andrey Smirnov)

  - Use data types that match actual imx6 PHY register width (Andrey
    Smirnov)

  - Mark imx6 suspend support with drvdata flags instead of checking
    variants (Andrey Smirnov)

  - Sleep instead of delay in imx6_pcie_enable_ref_clk() (Andrey Smirnov)

* remotes/lorenzo/pci/imx:
  PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()
  PCI: imx6: Use flags to indicate support for suspend
  PCI: imx6: Restrict PHY register data to 16-bit
  PCI: imx6: Simplify pcie_phy_poll_ack()
  PCI: imx6: Simplify bit operations in PHY functions
  PCI: imx6: Make use of BIT() in constant definitions
  PCI: dwc: imx6: Share PHY debug register definitions
  PCI: imx6: Remove PCIE_PL_PFLR_* constants
  PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change()
  PCI: imx6: Drop imx6_pcie_wait_for_link()
  PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()

  - Use generic config space reader in qcom (Marc Gonzalez)

  - Stop calling IRQ handler cleanup in dwc driver for invalid MSI IRQs
    (Jisheng Zhang)

  - Free dwc MSI target page when freeing MSI (Jisheng Zhang)

  - Fix dwc MSI leak in host init error path (Jisheng Zhang)

  - Use managed host bridge alloc to simplify dwc (Jisheng Zhang)

  - Save dwc root pci_bus pointer for use by .remove() methods (Jisheng
    Zhang)

  - Allow imx6 asynchronous probing (Lucas Stach)

* pci/dwc:
  PCI: imx6: Allow asynchronous probing
  PCI: dwc: Save root bus for driver remove hooks
  PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code
  PCI: dwc: Free MSI in dw_pcie_host_init() error path
  PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi()
  PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalid
  PCI: qcom: Use default config space read function

  - Restore R-Car PCIe link early in resume (Kazufumi Ikeda)

  - Fix Hyper-V PCI ejection memory leak (Dexuan Cui)

  - Cleanup Hyper-V PCI slots on module unload (Dexuan Cui)

  - Cleanup Hyper-V PCI slot on device removal to address a race (Dexuan
    Cui)

* remotes/lorenzo/pci/controller-fixes:
  PCI: hv: Add pci_destroy_slot() in pci_devices_present_work(), if necessary
  PCI: hv: Add hv_pci_remove_slots() when we unload the driver
  PCI: hv: Fix a memory leak in hv_eject_device_work()
  PCI: rcar: Add the initialization of PCIe link in resume_noirq()

  - Add Amazon Annapurna Labs PCIe host controller driver (Jonathan
    Chocron)

* pci/host/al:
  PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

  - Mark ATS on AMD Stoney Radeon R7 GPU broken to avoid IOMMU issues
    (Nikolai Kostrigin)

  - Mark Atheros AR9462 to avoid bus reset that locks up host machine
    (James Prestwood)

* pci/virtualization:
  PCI: Mark Atheros AR9462 to avoid bus reset
  PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken

  - Support all 255 PFF ports in switchtec driver (Wesley Sheng)

  - Fix unintentional switchtec MRPC event masking that degraded firmware
    update speed (Wesley Sheng)

* pci/switchtec:
  switchtec: Fix unintended mask of MRPC event
  switchtec: Increase PFF limit from 48 to 255

  - Disable Link Management interrupt during suspend to prevent immediate
    wakeup (Mika Westerberg)

* pci/portdrv:
  PCI/LINK: Disable bandwidth notification interrupt during suspend

  - Add a whitelist of Root Complexes known to support peer-to-peer DMA
    between Root Ports (Christian König)

* pci/peer-to-peer:
  PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root Complex

  - Mark expected switch fall-throughs (Gustavo A. R. Silva)

  - Remove unused pci_request_region_exclusive() (Johannes Thumshirn)

  - Fix x86 PCI IRQ routing table memory leak (Wenwen Wang)

  - Reset Lenovo ThinkPad P50 if firmware didn't do it on reboot (Lyude
    Paul)

  - Add and use pci_dev_id() helper to simplify PCI_DEVID() usage (touches
    several places outside drivers/pci/) (Heiner Kallweit)

  - Transition Mobiveil PCI maintenance to Karthikeyan M and Hou Zhiqiang
    (Subrahmanya Lingappa)

* pci/misc:
  MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCI
  platform/chrome: chromeos_laptop: use pci_dev_id() helper
  stmmac: pci: Use pci_dev_id() helper
  iommu/vt-d: Use pci_dev_id() helper
  iommu/amd: Use pci_dev_id() helper
  drm/amdkfd: Use pci_dev_id() helper
  powerpc/powernv/npu: Use pci_dev_id() helper
  r8169: use pci_dev_id() helper
  PCI: Add pci_dev_id() helper
  PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary
  x86/PCI: Fix PCI IRQ routing table memory leak
  PCI: Remove unused pci_request_region_exclusive()
  PCI: Mark expected switch fall-throughs

  - Remove unused mask_msi_irq(), unmask_msi_irq(), write_msi_msg(),
    __write_msi_msg() (Bjorn Helgaas)

* pci/msi:
  PCI/MSI: Remove unused mask_msi_irq() and unmask_msi_irq()
  PCI/MSI: Remove unused __write_msi_msg() and write_msi_msg()

  - Fix RPA and RPA DLPAR refcount issues (Tyrel Datwyler)

  - Stop exporting pci_get_hp_params() (Alexandru Gagniuc)

  - Simplify _HPP, _HPX parsing (Alexandru Gagniuc)

  - Add support for _HPX Type 3 settings (Alexandru Gagniuc)

  - Tell firmware we support _HPX Type 3 via _OSC (Alexandru Gagniuc)

* pci/hotplug:
  PCI/ACPI: Advertise _HPX Type 3 support via _OSC
  PCI/ACPI: Implement _HPX Type 3 Setting Record
  PCI/ACPI: Remove the need for 'struct hotplug_params'
  PCI/ACPI: Do not export pci_get_hp_params()
  PCI: rpaphp: Get/put device node reference during slot alloc/dealloc
  PCI: rpadlpar: Fix leaked device_node references in add/remove paths

  - Enable PCIe services for host controller drivers that use managed host
    bridge alloc (Jean-Philippe Brucker)

  - Add quirk to clear PCIe Retrain Link bit to work around Pericom bridge
    erratum (Stefan Mätje)

  - Add "external-facing" DT property to identify cases where we require
    IOMMU protection from untrusted devices (Jean-Philippe Brucker)

  - Support fixed bus numbers from bridge Enhanced Allocation capabilities
    (Subbaraya Sundeep)

* pci/enumeration:
  PCI: Assign bus numbers present in EA capability for bridges
  PCI: OF: Support "external-facing" property
  dt-bindings: Add "external-facing" PCIe port property
  PCI: Rework pcie_retrain_link() wait loop
  PCI: Work around Pericom PCIe-to-PCI bridge Retrain Link erratum
  PCI: Factor out pcie_retrain_link() function
  PCI: Init PCIe feature bits for managed host bridge alloc

  - Fix pci_aer_init() stub prototype for non-CONFIG_PCIEAER case (Jisheng
    Zhang)

* pci/aer:
  PCI/AER: Change pci_aer_init() stub to return void

Add Karthikeyan Mitran and Hou Zhiqiang as new maintainers of Mobiveil
controller driver.

Link: https://lore.kernel.org/linux-pci/1557229516-6870-1-git-send-email-l.subrahmanya@mobiveil.co.in


Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
[bhelgaas: update names/email addresses to match usage in git history]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>

Establishing a PCIe link can take a while; allow asynchronous probing so
that link establishment can happen in the background while other devices
are being probed.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

Currently DWC host does not support the remove callback, but nothing
prevents us from supporting it.

Save the root bus for clean up work in driver remove code paths to allow
DWC host drivers to implement their remove hook as, eg:

  static int foo_pcie_remove(struct platform_device *pdev)
  {
    ...
    pci_stop_root_bus(pp->root_bus);
    pci_remove_root_bus(pp->root_bus);
    dw_pcie_free_msi(pp);
    ...
  }

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

Use devm_pci_alloc_host_bridge() to simplify the error code path.  This
also fixes a leak in the dw_pcie_host_init() error path.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
CC: stable@vger.kernel.org	# v4.13+

If we ever did MSI-related initializations, we need to call
dw_pcie_free_msi() in the error code path.

Remove the IS_ENABLED(CONFIG_PCI_MSI) check for MSI init because
pci_msi_enabled() already has a stub for !CONFIG_PCI_MSI.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

To avoid a memory leak, free the page allocated for MSI IRQ in
dw_pcie_free_msi().

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

Check msi_irq variable before calling irq_set_chained_handler() and
irq_set_handler_data(), lest we call those functions for an invalid MSI
IRQ.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

Move the device class fudge to a proper fixup function, and remove
qcom_pcie_rd_own_conf() which has become useless.

dw_pcie_setup_rc() already did the right thing, but it's broken
on older qcom chips, such as 8064.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

The PCI specs say that peer-to-peer DMA should be supported between any two
devices that have a common upstream PCI-to-PCI bridge.  But devices under
different Root Ports don't share a common upstream bridge, and PCIe r4.0,
sec 1.3.1, says routing peer-to-peer transactions between Root Ports in the
same Root Complex is optional.

Many Root Complexes, including AMD ZEN, *do* support peer-to-peer DMA even
between Root Ports.  Add a whitelist and allow peer-to-peer DMA if both
participants are attached to a Root Complex known to support it.

Link: https://lore.kernel.org/linux-pci/20190418115859.2394-1-christian.koenig@amd.com


Signed-off-by: Christian König <christian.koenig@amd.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>

commit 834b9051 ("misc: pci_endpoint_test: Add support for
PCI_ENDPOINT_TEST regs to be mapped to any BAR") while adding
test_reg_bar in order to map PCI_ENDPOINT_TEST regs to be mapped to any
BAR failed to update test_reg_bar in pci_endpoint_test, resulting in
test_reg_bar having invalid value when used outside probe.

Fix it.

Fixes: 834b9051

 ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to
application registers. "PCIe Inbound Address Translation" section in
AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 as
reserved.

Configure pci_endpoint_test to use BAR_2 instead.

Also set alignment to 64K since "PCIe Subsystem Address Translation"
section in TRM indicates minimum ATU window size is 64K.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Certain platforms like K2G reguires the outbound ATU window to be
aligned. The alignment size is already present in mem->page_size.
Use the alignment size present in mem->page_size to configure an
aligned ATU window. In order to raise an interrupt, CPU has to write
to address offset from the start of the window unlike before where
writes were always to the beginning of the ATU window.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Configure the Resizable BAR capability to advertise the smallest size
(1MB) for a couple of reasons:

- Host side resource allocation of BAR fails for larger sizes
- Endpoint function driver does not allocate memory for all supported
  sizes in the Resizable BAR capability.

If and when there is a usecase required to add more flexibility using
the Resizable BAR capability, this can be revisited.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add PCIe EP support for AM654x Platforms in pci-keystone.c

Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/


Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add devicetree binding documentation for PCIe in EP mode present in
AM654 SoC.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

imx6_pcie_enable_ref_clk() is never called in atomic context, so
there's no need to use udelay(). Replace it with usleep_range().

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org

Now that driver data has flags variable that can be used to indicate
quirks/features supported we can switch the code to use it instead of
having a special function that does so based on variant alone. No
functional change intended.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org

PHY registers on i.MX6 are 16-bit wide, so we can get rid of explicit
masking if we restrict pcie_phy_read()/pcie_phy_write() to use 'u16'
instead of 'int'. No functional change intended.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org

Simplify pcie_phy_poll_ack() by incorporating shifting into constant
definition and convert the code to use 'bool'. No functional change
intended.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org