- Jun 10, 2015
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Joonyoung Shim authored
This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to 'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR of the MALI device. Signed-off-by:
Joonyoung Shim <jy0922.shim@samsung.com> [cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk] Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Hyungwon Hwang authored
This DIV_CPIF register must be stored when the system is suspended, and must be restored on system resume. This patch adds the register to the list of restored registers. Signed-off-by:
Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by:
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Chanwoo Choi authored
This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57} core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Signed-off-by:
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- Jun 06, 2015
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Dinh Nguyen authored
Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Dinh Nguyen authored
Sprinkled all through the platform clock drivers are code like this to fill the clock parent array: for (i = 0; i < num_parents; ++i) parent_names[i] = of_clk_get_parent_name(np, i); The of_clk_parent_fill() will do the same as the code above, and while at it, return the number of parents as well since the logic of the function is to the walk the clock node to look for the parent. Signed-off-by:
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Stephen Boyd authored
* clk-meson8b: clk: meson8b: Add support for Meson8b clocks clk: meson: Document bindings for Meson8b clock controller clk: meson: Add support for Meson clock controller
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Carlo Caione authored
This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs. Signed-off-by:
Carlo Caione <carlo@endlessm.com> Signed-off-by:
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Carlo Caione authored
Add documentation for the clock controller. Signed-off-by:
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Carlo Caione authored
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by:
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- Jun 05, 2015
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Uwe Kleine-König authored
Since commit 2893c379 ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
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James Liao authored
The size of clk_data should be the same as CLK_APMIXED_NR_CLK instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls). Signed-off-by:
James Liao <jamesjj.liao@mediatek.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
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Kevin Cernekee authored
When setting the PLL rates, check that: - VCO is within range - PFD is within range - PLL is disabled when postdiv is changed - postdiv2 <= postdiv1 Reviewed-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Kevin Cernekee <cernekee@chromium.org> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by:
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Ezequiel Garcia authored
Currently, when the rate is changed, the driver makes sure the PLL is enabled before doing so. This is done because the PLL cannot be locked while disabled. Once locked, the drivers returns the PLL to its previous enable/disable state. This is a bit cumbersome, and can be simplified. This commit reworks the .set_rate() functions for the integer and fractional PLLs. Upon rate change, the PLL is now locked only if it's already enabled. Also, the driver locks the PLL on .enable(). This makes sure the PLL is locked when enabled, and not locked when disabled. Signed-off-by:
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Ezequiel Garcia authored
This commit adds a pll_lock() helper making the code more readable. Cosmetic change only, no functionality changes. Signed-off-by:
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Chao Xie authored
Timer has external fast clock, and it is a mux clock. Add the timer clock type for timer driver. Signed-off-by:
Chao Xie <chao.xie@marvell.com> Signed-off-by:
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Chao Xie authored
The suggested value in the mmp2 manual is wrong. There are only 13 bits for numerator, but some suggested value has 14 bits. Fix the factor tabled and remove the unused items. Signed-off-by:
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Chao Xie authored
USB will drive clock from USB_PLL. Signed-off-by:
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- Jun 04, 2015
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Michael Turquette authored
Conflicts: drivers/clk/Kconfig
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Mike Looijmans authored
This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
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Boris Brezillon authored
Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Bintian Wang authored
Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by:
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by:
Bintian Wang <bintian.wang@huawei.com> Acked-by:
Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by:
Will Deacon <will.deacon@arm.com> Tested-by:
Tyler Baker <tyler.baker@linaro.org> Tested-by:
Kevin Hilman <khilman@linaro.org> Signed-off-by:
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Bintian Wang authored
Add the header file "hi6220-clock.h" used by both hi6220 clock driver and hi6220 device tree file. Suggested-by:
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Bintian Wang authored
__init markings on function prototypes are useless, so remove them. Suggested-by:
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- May 22, 2015
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Dinh Nguyen authored
The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by:
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Dinh Nguyen authored
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by:
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Shailendra Verma authored
Signed-off-by:
Shailendra Verma <shailendra.capricorn@gmail.com> Signed-off-by:
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Shailendra Verma authored
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Axel Lin authored
Remove a previously registered clock provider when unload the module. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Max Filippov <jcmvbkbc@gmail.com> Signed-off-by:
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- May 21, 2015
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Shailendra Verma authored
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Guo Zeng authored
This patch adds the fixed clocks of external crystal oscillators. Signed-off-by:
Guo Zeng <Guo.Zeng@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> [sboyd@codeaurora.org: Remove size-cells/address-cells] Signed-off-by:
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Zhiwu Song authored
the hardware node includes both clock and reset support, so it is named as "car". this patch implements Flexible clocks(mux, divider, gate), Selectable clock(mux, divider, gate), root clock(gate),leaf clock(gate), others. it also implements the reset controller functionality. Signed-off-by:
Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by:
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- May 20, 2015
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Ricky Liang authored
The variable init (struct clk_init_data) is allocated on the stack. We weren't initializing the .flags field, so it contains random junk, which can cause all kinds of interesting issues when the flags are parsed by clk_register. Signed-off-by:
Ricky Liang <jcliang@chromium.org> Acked-by:
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- May 16, 2015
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Rob Herring authored
Add initial clock support for Marvell PXA1928. The PXA1928 is a mobile SOC and is similar to other MMP/PXA series of SOCs, so a lot of the existing infrastructure is reused here. Currently the PLLs are just fixed clocks, and not all leaf clocks are implemented. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Rob Herring authored
This adds the clock binding documentation for the Marvell PXA1928 SOC. The PXA1928 has 3 clock control blocks for different subsystems of the chip. Signed-off-by:
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Chanwoo Choi authored
This patch shows the correct information for debugging when fail to set clock rate because original error message shows the error value instead of current clock rate. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by:
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- May 15, 2015
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Stephen Boyd authored
Having this Kconfig sourced outside the clk menu means the option is under the "Device Drivers" menu instead of the "Common Clock Framework" menu. Move it so that the bcm clock config options are in the right place. Cc: Alex Elder <elder@linaro.org> Signed-off-by: -
Stephen Boyd authored
drivers/clk/clk-u300.c:1175:13: warning: symbol 'u300_clk_init' was not declared. Should it be static? Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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