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  1. Aug 24, 2022
    • Conor Dooley's avatar
      riscv: dts: microchip: mpfs: remove pci axi address translation property · e4009c5f
      Conor Dooley authored 
      An AXI master address translation table property was inadvertently
added to the device tree & this was not caught by dtbs_check at the
time. Remove the property - it should not be in mpfs.dtsi anyway as
it would be more suitable in -fabric.dtsi nor does it actually apply
to the version of the reference design we are using for upstream.

Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3
Fixes: 528a5b1f

 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      e4009c5f
    • Conor Dooley's avatar
      riscv: dts: microchip: mpfs: remove bogus card-detect-delay · 2b55915d
      Conor Dooley authored 
      Recent versions of dt-schema warn about a previously undetected
undocumented property:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: mmc@20008000: Unevaluated properties are not allowed ('card-detect-delay' was unexpected)
        From schema: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

There are no GPIOs connected to MSSIO6B4 pin K3 so adding the common
cd-debounce-delay-ms property makes no sense. The Cadence IP has a
register that sets the card detect delay as "DP * tclk". On MPFS, this
clock frequency is not configurable (it must be 200 MHz) & the FPGA
comes out of reset with this register already set.

Fixes: bc47b221 ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107e

 ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      2b55915d
    • Conor Dooley's avatar
      riscv: dts: microchip: mpfs: remove ti,fifo-depth property · 72a05748
      Conor Dooley authored 
      Recent versions of dt-schema warn about a previously undetected
undocument property on the icicle & polarberry devicetrees:

arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: ethernet@20112000: ethernet-phy@8: Unevaluated properties are not allowed ('ti,fifo-depth' was unexpected)
        From schema: Documentation/devicetree/bindings/net/cdns,macb.yaml

I know what you're thinking, the binding doesn't look to be the problem
and I agree. I am not sure why a TI vendor property was ever actually
added since it has no meaning... just get rid of it.

Fixes: bc47b221 ("riscv: dts: microchip: add the sundance polarberry")
Fixes: 0fa6107e

 ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      72a05748
    • Conor Dooley's avatar
      riscv: dts: microchip: mpfs: fix incorrect pcie child node name · 3f67e699
      Conor Dooley authored 
      Recent versions of dt-schema complain about the PCIe controller's child
node name:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
            From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
Make the dts match the correct property name in the dts.

Fixes: 528a5b1f

 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      3f67e699
  3. Aug 18, 2022
    • Heinrich Schuchardt's avatar
      riscv: dts: microchip: correct L2 cache interrupts · 34fc9cc3
      Heinrich Schuchardt authored 
      The "PolarFire SoC MSS Technical Reference Manual" documents the
following PLIC interrupts:

1 - L2 Cache Controller Signals when a metadata correction event occurs
2 - L2 Cache Controller Signals when an uncorrectable metadata event occurs
3 - L2 Cache Controller Signals when a data correction event occurs
4 - L2 Cache Controller Signals when an uncorrectable data event occurs

This differs from the SiFive FU540 which only has three L2 cache related
interrupts.

The sequence in the device tree is defined by an enum:

    enum {
            DIR_CORR = 0,
            DATA_CORR,
            DATA_UNCORR,
            DIR_UNCORR,
    };

So the correct sequence of the L2 cache interrupts is

    interrupts = <1>, <3>, <4>, <2>;

[Conor]
This manifests as an unusable system if the l2-cache driver is enabled,
as the wrong interrupt gets cleared & the handler prints errors to the
console ad infinitum.

Fixes: 0fa6107e ("RISC-V: Initial DTS for Microchip ICICLE board")
CC: stable@vger.kernel.org # 5.15: e35b07a7

: riscv: dts: microchip: mpfs: Group tuples in interrupt properties
Signed-off-by: default avatarHeinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
      34fc9cc3
  5. Aug 13, 2022
  7. Aug 12, 2022