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    • Huacai Chen's avatar
      LoongArch: Fix hw_breakpoint_control() for watchpoints · 9730870b
      Huacai Chen authored
      
      
      In hw_breakpoint_control(), encode_ctrl_reg() has already encoded the
      MWPnCFG3_LoadEn/MWPnCFG3_StoreEn bits in info->ctrl. We don't need to
      add (1 << MWPnCFG3_LoadEn | 1 << MWPnCFG3_StoreEn) unconditionally.
      
      Otherwise we can't set read watchpoint and write watchpoint separately.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      9730870b
    • Huacai Chen's avatar
      LoongArch: Ensure FP/SIMD registers in the core dump file is up to date · 656f9aec
      Huacai Chen authored
      This is a port of commit 379eb01c
      
       ("riscv: Ensure the value
      of FP registers in the core dump file is up to date").
      
      The values of FP/SIMD registers in the core dump file come from the
      thread.fpu. However, kernel saves the FP/SIMD registers only before
      scheduling out the process. If no process switch happens during the
      exception handling, kernel will not have a chance to save the latest
      values of FP/SIMD registers. So it may cause their values in the core
      dump file incorrect. To solve this problem, force fpr_get()/simd_get()
      to save the FP/SIMD registers into the thread.fpu if the target task
      equals the current task.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
      656f9aec