- Nov 04, 2009
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Alex Deucher authored
Noticed by Andre on IRC. Also fix up some minor whitespace issues. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
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Dave Airlie authored
The Lenovo W500 laptop hangs inside an SMI on brightness changes, I thought it just needed the VGA disable but it turned out to require slightly more work, setting the MC locations up just like the IGP chip requirements seems to make it all happy again and I can boot and play with brightness. We should probably just do this for all chips and give up the VRAM at 0x0 idea, it never seems to buy us anything but pain. Signed-off-by: -
Dave Airlie authored
Once kms is enabled we don't need these, and it causes a problem with the Lenovo W500 ACPI brightness implementation, it hangs in a loop inside an SMI. Signed-off-by: -
Alex Deucher authored
Immediate readback seems faulty on some chips. I suspect it takes a while to get through the fifo to the actual register backbone. There's no need to read it back, so, just write the driver's copy of the register's value directly. Should fix bug 24535 and possibly 24218 Signed-off-by:
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Dave Airlie authored
When we are evicting from VRAM->RAM we allocate the ttm object, but we don't set the caching policy on it before blitting into it. This means on AGP we end up blitting into cached pages, and the CPU later flushes out on top of them. This was mostly seen as font corruption. The other question is why we don't evict VRAM->GTT in a lot of cases, this would save us some cache transitions since a lot of objects that are evicted from VRAM will probably end up being pulled back in a few operations later, and evicting them to system memory involves 2 unnecessary cache transitions. Signed-off-by:
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- Oct 28, 2009
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Dave Airlie authored
This fixes suspend/resume on my rc410 motherboard, it restores the memory controller setup before posting the GPU, since it seems to need the MC_FB_LOCATION setup correctly. Signed-off-by: -
Alex Deucher authored
Doesn't have a tv-out port Signed-off-by:
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Alex Deucher authored
Make sure we have an LVDS encoder before casting enc_priv. [airlied: also fix two missing cpu_to_le16 casts we noticed on irc] Signed-off-by:
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James Simmons authored
I believe this is a typo. Signed-off-by: -
Mathias Fröhlich authored
Make the struct card_info, which is a per struct radeon_device dataset, a struct member of the radeon device instead of a static per kernel module value. This should avoid potential problems with two radeon cards installed in one system. Signed-off-by:
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Alex Deucher authored
DVO in 12 bit mode (which seems to be the most common config) requires 2x ppll. Fixes fdo bug 21857. Signed-off-by:
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Alex Deucher authored
Limiting the pll output range is a good thing generally as it limits the number of possible pll combinations for a given frequency presumably to the ones that work best on each card. That's why the limits are in the bios tables. However, certain duallink DVI monitors seem to like pll combinations that would be limited by this at least on pre-DCE 3.0 r6xx hardware. This might need to be adjusted per family or per clock range in the future. See fdo bug 24727. Signed-off-by:
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- Oct 26, 2009
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Alex Deucher authored
Try to enable msi on chips that support it. Signed-off-by:
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Alex Deucher authored
Spread spectrum is a periodic disturbance added to the feedback divider to change the pixel clock periodically to reduce interference. Only enabled on LVDS. v2: add support for r4xx and fix DCE 3 Signed-off-by:
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Alex Deucher authored
The *_HIGH regs are reversed. The secondary ones are in the primary block and vice versa. We currently only use a 32 bit internal address, so these are 0 for now. Signed-off-by:
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Robert Noland authored
This patch only changes this is the swap path, where it doesn't loop. Signed-off-by:
Robert Noland <rnoland@2hip.net> Signed-off-by:
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Robert Noland authored
- Reduce the chance of error and avoid a bit of overhead. - Use switch to assign color and format Signed-off-by:
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Mathias Fröhlich authored
Where supported use ulMinPixelClockPLL_Output rather than usMinPixelClockPLL_Output for pll_out_min. This seems to improve pll selection on some boards. Signed-off-by:
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Alex Deucher authored
doesn't have a tv-out port Signed-off-by:
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Alex Deucher authored
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Mathias Fröhlich authored
The problem boils down to the order when the bit11 of the texture size is or'ed to the original width. In the end each mipmap level has the same width or height because of that 11 bit is ored to the scaled down lod with and thus blows up the size again to the full size or more due to the power of two rounding afterwards. The attached patch changes this order so that the texture sizes are computed correct. Also the on error the yet missing inputs to the size computation are printed which helped me to find out where it really breaks. Signed-off-by:
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Dave Airlie authored
This sets the fbcon to use TRUECOLOR by default, it then only modifies the pseudo palette for fbcon, and only touches the real palette when in 8-bit pseudo color mode. Signed-off-by:
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- Oct 16, 2009
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Alex Deucher authored
Original radeon didn't have a connector table in the bios. Check for the CRT table and if we have one, add a VGA connector. Signed-off-by:
Dave Airlie <airlied@linux.ie>
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Alex Deucher authored
Need to check the return type for the quirk function to decide whether we add the connectors and encoders. Signed-off-by:
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Zhao Yakui authored
Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by:
Zhao Yakui <yakui.zhao@intel.com> Signed-off-by:
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Matt Turner authored
Signed-off-by:
Matt Turner <mattst88@gmail.com> Signed-off-by:
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Alex Deucher authored
fixes fdo bug 24496 Signed-off-by:
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Alex Deucher authored
D1MODE_INTERLEAVE_EN was getting set in some cases in the encoder quirks function due to the changes in 5a9bcacc Signed-off-by:
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Alex Deucher authored
Based partly on a patch from Christian Koenig <deathsimple@vodafone.de> - fix several memory leaks in radeon_connector->edid handling - store edid in radeon_connector->edid in detect() or get_modes() - switch hdmi detect code to use radeon_connector->edid - add support for oem boards multiple connectors that share a ddc line. - short circuit lvds_detect() if have a stored edid Signed-off-by:
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- Oct 15, 2009
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Alex Deucher authored
- crtc 0 routing was wrong - need to clear various timing bits in FP_GEN_CNTL - need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1 Signed-off-by:
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Alex Deucher authored
radeon_encoder->active_device defines the active routing between the encoder and connector. The encoder fixup and dpms functions need to know the active_device to function properly. Setting active_device in the prepare hook was too late in some cases. Signed-off-by:
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- Oct 13, 2009
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Alex Deucher authored
drm modes are objects with indentifiers. Make sure to preserve the mode id when copying mode params. Signed-off-by:
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- Oct 12, 2009
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Dave Airlie authored
With the adjust table introduction, we need to fill out index before getting the table version. Signed-off-by: -
Dave Airlie authored
This reverts commit 49c458e5 . It seems to have some side effects in the non-kms cases. Signed-off-by:
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Alex Deucher authored
In case the system has bad native mode info but valid edid. Signed-off-by:
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Alex Deucher authored
This reduces the number of mode format conversions needed and makes native panel mode support cleaner. Signed-off-by:
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Alex Deucher authored
- clean up tv timing handling - unify SetCRTC_Timing and SetCRTC_UsingDTDTiming Signed-off-by:
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Alex Deucher authored
DCE3+ has an AdjustDisplayPll that will adjust the pixel clock accordingly based on the encoder/transmitter to handle special hw requirements. Signed-off-by:
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Alex Deucher authored
Based on recommendation from bios docs. Signed-off-by:
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