1. Sep 07, 2017
  2. Sep 05, 2017
  3. Aug 29, 2017
    • Stefan Roese's avatar
      dmaengine: altera: Use macros instead of structs to describe the registers · 6084fc2e
      Stefan Roese authored
      
      
      This patch moves from a struct declaration for the DMA controller
      registers to macros with offests to the base address. This is mainly
      done to remove the sparse warnings, since the function parameter of
      ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct
      members. With this patch applied, no sparse warning is seen anymore.
      
      Please note that the struct for the descriptors is still kept in place,
      as the code largely accesses the struct members as internal variables
      before the complete struct is copied into the descriptor FIFO of the
      DMA controller.
      
      Additionally this patch also removes two warnings "variable xxx set but
      not used" seen when compiling with "W=1". The registers need to be read
      to flush the response FIFO, but nothing needs to be done with them. So
      the code is correct here and the warning is a false one.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      6084fc2e
    • Alexander Smirnov's avatar
      dmaengine: ti-dma-crossbar: Fix dra7 reserve function · a2f6721b
      Alexander Smirnov authored
      
      
      DMA crossbar uses 'xbar->dma_inuse' variable to manage allocated routes.
      Each bit represents respective DMA channel. If the channel is free, bit
      is set to '0', if channel is allocated, bit should be set to '1'.
      
      In reserve function, the bits for requested DMA channels are cleared, so
      they are not really reserved, but freed and become ready for allocation.
      
      Signed-off-by: default avatarAlexander Smirnov <asmirnov@ilbers.de>
      Acked-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      a2f6721b
  4. Aug 28, 2017
  5. Aug 25, 2017
  6. Aug 24, 2017
  7. Aug 23, 2017
  8. Aug 22, 2017