- Mar 16, 2020
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Peng Fan authored
Per binding doc fsl,aips-bus.yaml, compatible and reg is required. And for reg, the AIPS configuration space should be used, not all the AIPS bus space. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Anson Huang authored
i.MX8MN shares same thermal sensor with i.MX8MM, add thermal zone support for i.MX8MN. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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- Mar 12, 2020
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Anson Huang authored
Add thermal zone and tmu node to support i.MX8MM thermal driver, ONLY cpu thermal zone is supported, and cpu cooling is also added. Signed-off-by:
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- Mar 11, 2020
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Alifer Moraes authored
i.MX8MQ Phanbell board uses Realtek RTL8211FD as Ethernet PHY. Its datasheet states that the proper post reset duration should be at least 50 ms. Fixes: f34d4bfa ("arm64: dts: imx8mq-phanbell: Add support for ethernet") Signed-off-by:
Alifer Moraes <alifer.wsdm@gmail.com> Signed-off-by:
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Adam Ford authored
Pull in downstream patch from NXP repository to enable fspi device. Signed-off-by:
Han Xu <han.xu@nxp.com> Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
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Silvano di Ninno authored
crypto child nodes should use the "jr" name (without an index), as indicated in the DT binding. Signed-off-by:
Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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Kuldeep Singh authored
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected on different buses, only one flash can be probed at a time. Add fspi node properties aligned with LX2160A-RDB fspi properties. Signed-off-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by:
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Kuldeep Singh authored
Update fspi node compatibles of LX2160A-RDB to "jedec,spi-nor" for automatic detection of flash. This also helps in fixing below warning: spi-nor spi0.0: found mt35xu512aba, expected m25p80 spi-nor spi0.1: found mt35xu512aba, expected m25p80 Signed-off-by:
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Vitor Massaru Iha authored
It was based on Google Source Code for Coral Edge TPU Mendel release: https://coral.googlesource.com/linux-imx/ It was tested on Coral Dev Board using this command: sudo stress --cpu 4 --timeout 3600 Signed-off-by:
Vitor Massaru Iha <vitor@massaru.org> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
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Hou Zhiqiang authored
Add the iommu-map property to the pci nodes so that the firmware fixes it up with the required values thus enabling iommu for devices connected over pci. Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by:
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Anson Huang authored
Enable pca6416 on i.MX8MP EVK board's i2c3 bus. Signed-off-by:
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Anson Huang authored
Enable i2c3 for i.MX8MP EVK board. Signed-off-by:
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Anson Huang authored
Enable pca6416 on i.MX8MN EVK board's i2c3 bus. Signed-off-by:
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Anson Huang authored
Enable i2c3 for i.MX8MN EVK board. Signed-off-by:
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Martin Kepplinger authored
The IMU chip on the librem5-devkit is not mounted at the "natural" place that would match normal phone orientation (see the documentation for the details about what that is). Since the lsm9ds1 driver supports providing a mount matrix, we can describe the orientation on the board in the dts: Create a right-handed coordinate system (x * -1; see the datasheet for the axis) and rotate 180 degrees around the y axis because the device sits on the back side from the display. Signed-off-by:
Martin Kepplinger <martin.kepplinger@puri.sm> Reviewed-by:
Marco Felsch <m.felsch@pengutronix.de> Signed-off-by:
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Angus Ainslie (Purism) authored
The poly fuses can handle 6V 4Amps so incease the kernel limts to 5V 3.5Amps. Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca> Signed-off-by:
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Angus Ainslie (Purism) authored
By adding broken-cd to the usdhc2 stanza the Redpine card can be detected when the HKS is turned off and on. Signed-off-by:
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Angus Ainslie (Purism) authored
Specify which regulator is used for cpufreq DVFS. Signed-off-by:
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Angus Ainslie (Purism) authored
Connect the WoWWAN signal to a gpio key to wake up the system from suspend. Signed-off-by:
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Angus Ainslie (Purism) authored
Add the simcom SIM7100 modem and the sai6 interface that connects it. Signed-off-by:
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Angus Ainslie (Purism) authored
Describe the sgtl5000 of the librem 5 devkit in devicetree. Signed-off-by:
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Angus Ainslie (Purism) authored
Without a VBUS supply the dwc3 driver won't go into otg mode. Fixes: eb4ea085 ("arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit") Signed-off-by:
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Rabeeh Khoury authored
This patch adds 4 eeprom support on i2c mux channel #0 - 1. Bootable 512Kbit eeprom at address 0x50. 2. Memory SO-DIMMs SPD channels at 0x51 (upper SO-DIMM) and 0x53. 3. 2Kb eeprom at 0x57 will be used by SolidRun to hold manufacturing data. Signed-off-by:
Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Russell King authored
Add support for the LTC3882 regulator so that the hardware monitoring can be used with this device. This regulator provides the 0.78V supply for the LX2160A. Signed-off-by:
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Anson Huang authored
Add src node to support i.MX8MP reset controller. Signed-off-by:
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Anson Huang authored
Node name should be generic, use "pinctrl" instead of "iomuxc" for all i.MX8M SoCs. Signed-off-by:
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André Draszik authored
On i.MX8MM, the SNVS requires a clock. This is similar to the clock bound to the SNVS RTC node, but if the SNVS RTC driver isn't enabled, then SNVS doesn't work, and as such the pwrkey driver doesn't work (i.e. hangs the kernel, as the clock isn't enabled). Also see commit ec2a844e ("ARM: dts: imx7s: add snvs rtc clock") for a similar fix. Signed-off-by:
André Draszik <git@andred.net> Signed-off-by:
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André Draszik authored
On i.MX8MM, the SNVS requires a clock. This is similar to the clock bound to the SNVS RTC node, but if the SNVS RTC driver isn't enabled, then SNVS doesn't work, and as such the pwrkey driver doesn't work (i.e. hangs the kernel, as the clock isn't enabled). Also see commit ec2a844e ("ARM: dts: imx7s: add snvs rtc clock") for a similar fix. Signed-off-by:
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Horia Geantă authored
Add node for CAAM - Cryptographic Acceleration and Assurance Module. Signed-off-by:
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Anson Huang authored
Add i.MX8QXP CPU thermal zone support. Signed-off-by:
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Michael Walle authored
Since commit b9213899d2b0 ("arm64: dts: ls1028a: disable all enetc ports by default") all the network ports are disabled by default. This makes sense, but now we have to enable them explicitly in the boards. Do so for the sl28 module. Since we are at it. Make sure the second port is only enabled for the variant 4 of the module. Variant 3 has only one network port. Signed-off-by:Michael Walle <michael@walle.cc> Signed-off-by:
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Claudiu Manoil authored
Link the switch PHY nodes to the central MDIO controller PCIe endpoint node on LS1028A (implemented as PF3) so that PHYs are accessible via MDIO. Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514 quad PHY is capable of in-band-status. The PHYs are used in poll mode due to an issue with the interrupt line on current revisions of the LS1028A-RDB board. Signed-off-by:
Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Claudiu Manoil authored
Add the switch device node, available on PF5, so that the switch port sub-nodes (net devices) can be linked to corresponding board specific phy nodes (external ports) or have their link mode defined (internal ports). The switch device features 6 ports, 4 with external links and 2 internally facing to the LS1028A SoC and connected via fixed links to 2 internal ENETC Ethernet controller ports. Add the corresponding ENETC host port device nodes, mapped to PF2 and PF6 PCIe functions. Since the switch only supports tagging on one CPU port, only one port pair (swp4, eno2) is enabled by default and the other, lower speed, port pair is disabled to prevent the PCI core from probing them. If enabled, swp5 will be a fixed-link slave port. DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the 1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to <&enetc_port3> and moving it under port5, but in that case enetc_port2 should not be disabled, because it is the hardware owner of the Felix PCS and disabling its memory would result in access faults in the Felix DSA driver. All ports are disabled by default, including the CPU port, and need to be enabled on a per-board basis. The phy-mode binding of the internal ENETC ports was modified from "gmii" to "internal" to match the phy-mode of the internal-facing switch ports connected to them. The ENETC driver does not perform any phy_mode validation anyway, so the change is only cosmetic. Also, enetc_port2 is defined as a fixed-link 1000 Mbps port even though it is 2500 Mbps (as can be seen by the fact that it is connected to mscc_felix_port4). The fact that it is currently defined as 1000 Mbps is an artifact of its PHYLIB implementation instead of PHYLINK (the former can't describe a fixed-link speed higher than what swphy can emulate from the Clause 22 MDIO spec). The switch's INTB interrupt line signals: - PTP TX timestamp availability - TSN Frame Preemption And don't forget to enable the 4MB BAR4 in the root complex ECAM space, where the switch registers are mapped. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by:
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Vladimir Oltean authored
There are few boards that enable all ENETC ports, so instead of having board DTs disable them, do so in the DTSI and have the boards enable the ports they use. Signed-off-by:
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Vladimir Oltean authored
This specifier overrides the interrupt specifier with 3 cells from gic (/interrupt-controller@6000000), but in fact ENETC is not an interrupt controller, so the property is bogus. Interrupts used by the children of the ENETC RCIE must use the full 3-cell specifier required by the GIC. The issue has no functional consequence so there is no real reason to port the patch to stable trees. Fixes: 927d7f85 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints") Signed-off-by:
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- Feb 24, 2020
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Anson Huang authored
According to latest datasheet Rev.0, 10/2019, there is restriction as below: "If VDD_SOC/GPU/DDR = 0.95V, then VDD_ARM must be >= 0.95V." As by default SoC is running at OD mode(VDD_SOC = 0.95V), so VDD_ARM 1.2GHz OPP's voltage should be increased to 0.95V. Signed-off-by:
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Anson Huang authored
System counter timer is necessary as broadcast timer for cpu-idle, add support for it. Signed-off-by:
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Anson Huang authored
i.MX8MP EVK board has a GPIO LED to indicate status, add support for it. Signed-off-by:
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Alifer Moraes authored
imx8mq-evk has a GPIO connected to AR8031 Ethernet PHY's reset pin. Describe it in the device tree, following phy's datasheet reset duration of 10ms. Tested booting via NFS. Signed-off-by:
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Alifer Moraes authored
imx8mm-evk has a GPIO connected to AR8031 Ethernet PHY's reset pin. Describe it in the device tree, following phy's datasheet reset duration of 10ms. Tested booting via NFS. Signed-off-by:
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