- Jun 22, 2021
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Wesley Chalmers authored
[WHY] extended_end_address can only be calculated from the extended_address and extended_size Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Martin Tsai authored
[Why] The voltage swing has to start from the minimum level when transmit TPS1 over Main-Link in clock recovery sequence. The lane settings from current design will inherit the existing VS/PE values that could be adjusted by Repeater X, and to use the adjusted voltage swing level in Repeater X-1 or DPRX could violate DP specs. [How] To reset VS from lane settings after LTTPRs have been trained to meet the requirement. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Nikola Cornij authored
[why] Some timings with a large VBlank cause the value to overflow the register related, while also producing other wrong values in DML output. [how] Clamp VStartup at the DCN3.1 maximum value Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Aric Cyr authored
[Why] When video plane is rotate the cursor position is incorrect and not matching the desktop location. [How] When a plane is rotated 90 or 270 degrees, the src_rect.width and height should be swapped when determining the scaling factor compared to the dst_rect. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Yifan Zhang authored
This reverts commit 63100310 . Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may cause some APUs fail to enter gfxoff in certain user cases. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
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Yifan Zhang authored
This reverts commit 1ba7b24b . Reason for revert: Side effect of enlarging CP_MEC_DOORBELL_RANGE may cause some APUs fail to enter gfxoff in certain user cases. Signed-off-by:
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- Jun 19, 2021
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Michel Dänzer authored
Once drm_framebuffer_init has returned 0, the framebuffer is hooked up to the reference counting machinery and can no longer be destroyed with a simple kfree. Therefore, it must be called last. If drm_framebuffer_init returns 0 but its caller then returns non-0, there will likely be memory corruption fireworks down the road. The following lead me to this fix: [ 12.891228] kernel BUG at lib/list_debug.c:25! [...] [ 12.891263] RIP: 0010:__list_add_valid+0x4b/0x70 [...] [ 12.891324] Call Trace: [ 12.891330] drm_framebuffer_init+0xb5/0x100 [drm] [ 12.891378] amdgpu_display_gem_fb_verify_and_init+0x47/0x120 [amdgpu] [ 12.891592] ? amdgpu_display_user_framebuffer_create+0x10d/0x1f0 [amdgpu] [ 12.891794] amdgpu_display_user_framebuffer_create+0x126/0x1f0 [amdgpu] [ 12.891995] drm_internal_framebuffer_create+0x378/0x3f0 [drm] [ 12.892036] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] [ 12.892075] drm_mode_addfb2+0x34/0xd0 [drm] [ 12.892115] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] [ 12.892153] drm_ioctl_kernel+0xe2/0x150 [drm] [ 12.892193] drm_ioctl+0x3da/0x460 [drm] [ 12.892232] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] [ 12.892274] amdgpu_drm_ioctl+0x43/0x80 [amdgpu] [ 12.892475] __se_sys_ioctl+0x72/0xc0 [ 12.892483] do_syscall_64+0x33/0x40 [ 12.892491] entry_SYSCALL_64_after_hwframe+0x44/0xae Fixes: f258907f "drm/amdgpu: Verify bo size can fit framebuffer size on init." Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Wan Jiabing authored
Fix coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c: 55:12-42: duplicated argument to && or || Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Signed-off-by:
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Shaokun Zhang authored
Function 'dpp1_full_bypass' is declared twice, so remove the repeated declaration and unnessary blank line. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by:
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Gustavo A. R. Silva authored
In preparation to enable -Wimplicit-fallthrough for Clang, fix the following warning by replacing a /* fall through */ comment with the new pseudo-keyword macro fallthrough: rivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:672:4: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: ^ Notice that Clang doesn't recognize /* fall through */ comments as implicit fall-through markings, so in order to globally enable -Wimplicit-fallthrough for Clang, these comments need to be replaced with fallthrough; in the whole codebase. Link: https://github.com/KSPP/linux/issues/115 Reviewed-by:Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Pu Lehui authored
GCC reports the following warning with W=1: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.c:70:13: warning: variable ‘dc’ set but not used [-Wunused-but-set-variable] 70 | struct dc *dc = NULL; | ^~ This variable is not used in function, this commit remove it to fix the warning. Reviewed-by:Pu Lehui <pulehui@huawei.com> Signed-off-by:
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Pu Lehui authored
GCC reports the following warning with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3635:17: warning: variable ‘status’ set but not used [-Wunused-but-set-variable] 3635 | enum dc_status status = DC_ERROR_UNEXPECTED; | ^~~~~~ The variable should be used for error check, let's fix it. Reviewed-by: -
xinhui pan authored
To avoid any list corruption. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Bokun Zhang authored
In the past, we use MMSCH to determine whether a VCN is enabled or not. This is not reliable since after a FLR, MMSCH may report junk data. It is better to use IP discovery data. Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by:
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Yifan Zhang authored
Pagelist is no long used in amdgpu_gart_bind. Remove it. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Yifan Zha authored
[Why] sriov vf send unsupported SMU message lead to fail. [How] disable related messages in sriov. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Acked-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Stanley.Yang authored
Use SMU to update the bad pages rather than directly accessing the EEPROM from the driver. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Ashish Pawar authored
Modify power brake enablement sequence on Aldebaran Signed-off-by:
Ashish Pawar <ashish.pawar@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Stanley.Yang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Darren Powell authored
replaced snprintf usage in amdgpu_pm.c with sysfs_emit fixed warning on comparing int with uint32_t in amdgpu_get_pp_num_states() == Test == AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 10` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > scnprintf.test.log FILES="pp_num_states pp_od_clk_voltage pp_features pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_vclk pp_dpm_dclk pp_dpm_dcefclk pp_power_profile_mode " for f in $FILES do echo === $f === >> scnprintf.test.log cat $HWMON_DIR/device/$f >> scnprintf.test.log done Signed-off-by:Darren Powell <darren.powell@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Eric Huang authored
Fix non-coherent bit of iolink properties flag which always is 0. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
Recently, we added support for an experimental feature named Freesync video; for more details on that, refer to: commit 6f59f229 ("drm/amd/display: Skip modeset for front porch change") commit d10cd527 ("drm/amd/display: Add freesync video modes based on preferred modes") commit 0eb1af2e ("drm/amd/display: Add module parameter for freesync video mode") Nevertheless, we did not document it in detail in our driver. This commit introduces a kernel-doc and expands the module parameter description. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Alex Deucher authored
Probably a rebase leftover. This doesn't apply to SR-IOV, and the non-SR-IOV code below it already handles this properly. Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why] Current watermarks end up programming lowers watermarks which results in screen flickering and underflow for certain modes like 1440p. [How] Add 11us to stutter exit & stutter enter plus exit watermark. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Stanley.Yang authored
Signed-off-by:
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xinhui pan authored
Because TTM do page counting on userptr BOs which is actually not needed. To avoid that, lets set TTM_PAGE_FLAG_SG after tt_create and before tt_populate. Signed-off-by:
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- Jun 18, 2021
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Dave Airlie authored
Merge tag 'amd-drm-next-5.14-2021-06-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-16: amdgpu: - Aldebaran fixes - Expose asic independent throttler status - BACO fixes for navi1x - Smartshift fixes - Misc code cleanups - RAS fixes for Sienna Cichlid - Gamma verificaton fixes - DC LTTPR fixes - DP AUX timeout handling fixes - GFX9, 10 powergating fixes amdkfd: - TLB flush fixes when using SDMA - Locking fixes - SVM fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210617031719.4013-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'mediatek-drm-next-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.14 1. Add MT8167 HDMI support 2. Fix PM reference leak 3. Add MT8183 DPI dual edge support Signed-off-by:
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- Jun 16, 2021
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Wan Jiabing authored
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c:917:56-57: pstate_enabled: first occurrence line 935, second occurrence line 937 Reviewed-by:
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Amber Lin authored
Calling free_mqd inside of destroy_queue_nocpsch_locked can cause a circular lock. destroy_queue_nocpsch_locked is called under a DQM lock, which is taken in MMU notifiers, potentially in FS reclaim context. Taking another lock, which is BO reservation lock from free_mqd, while causing an FS reclaim inside the DQM lock creates a problematic circular lock dependency. Therefore move free_mqd out of destroy_queue_nocpsch_locked and call it after unlocking DQM. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
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Felix Kuehling authored
This should fix a kernel LOCKDEP warning on Vega10: [ 149.416604] ================================ [ 149.420877] WARNING: inconsistent lock state [ 149.425152] 5.11.0-kfd-fkuehlin #517 Not tainted [ 149.429770] -------------------------------- [ 149.434053] inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage. [ 149.440059] swapper/3/0 [HC1[1]:SC0[0]:HE0:SE1] takes: [ 149.445198] ffff9ac80e005d68 (&adev->vm_manager.pasid_lock){?.+.}-{2:2}, at: amdgpu_vm_get_task_info+0x25/0x90 [amdgpu] [ 149.456252] {HARDIRQ-ON-W} state was registered at: [ 149.461136] lock_acquire+0x242/0x390 [ 149.464895] _raw_spin_lock+0x2c/0x40 [ 149.468647] amdgpu_vm_handle_fault+0x44/0x380 [amdgpu] [ 149.474187] gmc_v9_0_process_interrupt+0xa8/0x410 [amdgpu] ... Signed-off-by:Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Yifan Zhang authored
If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by:
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Yifan Zhang authored
If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by:
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Nirmoy Das authored
Move shadow_list to struct amdgpu_bo_vm as shadow BOs are part of PT/PD BOs. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Nirmoy Das authored
Make provision to pass different ttm BO destroy callback while creating a amdgpu_bo. Signed-off-by:
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Nirmoy Das authored
Page table entries are now in embedded in VM BO, so we do not need struct amdgpu_vm_pt. This patch replaces struct amdgpu_vm_pt with struct amdgpu_vm_bo_base. Signed-off-by:
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Hawking Zhang authored
For ASICs that need to load sys_drv_aux and sos_aux, the sys_start_addr is not the start address of psp ucode array because the sys_drv_aux and sos_aux actaully located at the end of the ucode array, instead, the psp ucode arrary start address should be sos_hdr + sos_hdr_offset. Signed-off-by:
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Felix Kuehling authored
When some GPUs don't support SVM, don't disabe it for the entire process. That would be inconsistent with the information the process got from the topology, which indicates SVM support per GPU. Instead disable SVM support only for the unsupported GPUs. This is done by checking any per-device attributes against the bitmap of supported GPUs. Also use the supported GPU bitmap to initialize access bitmaps for new SVM address ranges. Don't handle recoverable page faults from unsupported GPUs. (I don't think there will be unsupported GPUs that can generate recoverable page faults. But better safe than sorry.) Signed-off-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] DP LL Compliance tests require that the first DPCD transactions after a hotplug have a timeout interval of 3.2 ms. In cases where LTTPR is disabled, this means that the first reads from DP_SET_POWER and DP_DPCD_REV must have an extended timeout. Signed-off-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] When changing the DISPCLK_WDIVIDER value from 126 to 127, the change in clock rate is too great for the FIFOs to handle. This can cause visible corruption during clock change. HW has handed down this register sequence to fix the issue. [HOW] The sequence, from HW: a. 127 -> 126 Read DIG_FIFO_CAL_AVERAGE_LEVEL FIFO level N = DIG_FIFO_CAL_AVERAGE_LEVEL / 4 Set DCCG_FIFO_ERRDET_OVR_EN = 1 Write 1 to OTGx_DROP_PIXEL for (N-4) times Set DCCG_FIFO_ERRDET_OVR_EN = 0 Write DENTIST_DISPCLK_RDIVIDER = 126 Because of frequency stepping, sequence a can be executed to change the divider from 127 to any other divider value. b. 126 -> 127 Read DIG_FIFO_CAL_AVERAGE_LEVEL FIFO level N = DIG_FIFO_CAL_AVERAGE_LEVEL / 4 Set DCCG_FIFO_ERRDET_OVR_EN = 1 Write 1 to OTGx_ADD_PIXEL for (12-N) times Set DCCG_FIFO_ERRDET_OVR_EN = 0 Write DENTIST_DISPCLK_RDIVIDER = 127 Because of frequency stepping, divider must first be set from any other divider value to 126 before executing sequence b. Signed-off-by:
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