- Jul 07, 2022
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Dmitry Baryshkov authored
Other PHYs tables directly reference FLL registers without using reglayout. Define corresponding registers to be used by msm8996 PHY tables and use them directly. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-28-dmitry.baryshkov@linaro.org Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.19's qcom,kona-qmp-usb3.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.19's qcom,usb3-11nm-qmp-combo.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-5.4's qcom,usb3-5nm-qmp-uni.h - msm-5.4's qcom,usb3-5nm-qmp-combo.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.19's qcom,kona-qmp-usb3.h The 0x1a0 register name was corrected, verified via msm-4.14's qcom,sdxprairie-qmp-usb3.h. Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-4.4's phy-qcom-ufs-qmp-v3.h Signed-off-by:
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Dmitry Baryshkov authored
Add missing registers, verified against: - msm-3.18's phy-qcom-ufs-qmp-14nm.h - msm-3.18's mdss-hdmi-pll-8996.c - msm-5.4's ep_pcie_phy.h Signed-off-by:
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Dmitry Baryshkov authored
Several registers defined in the PCS V3 namespace in reality belong to the PCS_UFS V3 register space. Move them to the separate header and rename them to explicitly mention PCS_UFS. While we are at it, correct one register in the msm8998_usb3_pcs_tbl table to use PCS register name. Signed-off-by:
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Dmitry Baryshkov authored
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by:
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Dmitry Baryshkov authored
Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by:
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Dmitry Baryshkov authored
Move PCIE QHP registers to the separate header. QHP is a sepecial PHY kind used on sdm845 to drive one of PCIe links. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V5 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V4 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V3 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move PCS V2 registers to the separate header. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES PLL registers to the separate header. This register set is unique for the IPQ PCIe Gen3 PHYs. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V5 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V4 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V3 registers to the separate headers. Signed-off-by:
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Dmitry Baryshkov authored
Move QSERDES V2 registers to the separate header. Signed-off-by:
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Dmitry Baryshkov authored
PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the IPQ6018 and IPQ8074 tables and drop the custom PCS_COM_*/PCS_PCIE* names. Signed-off-by:
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Dmitry Baryshkov authored
Rename QMP V2 PCS registers to follow the usual pattern of QPHY_V2_PCS_*. Signed-off-by:
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Dmitry Baryshkov authored
Replace separate defines for QMP V2 PHY for PCIe gen3 ports. They are equivalent to the QSERDES_V4_ symbols. Signed-off-by:
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Dmitry Baryshkov authored
Follow the example of other PCIe PHYs and use separate pcs_misc region to access PCS_PCIE_* resources. Signed-off-by:
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Dmitry Baryshkov authored
Different QMP USB PHYs might have different offset from PCS to PCS_USB register space, but the same PCS_USB register layout. Add separate PCS_USB region space and merge related PCS_USB definitions. Signed-off-by:
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Dmitry Baryshkov authored
The msm8996_ufs_serdes_tbl table contains write to QPHY_POWER_DOWN_CONTROL, however this register doesn't belong to the QSERDES register space. Also the PHY power down is already handled in the qcom_qmp_phy_ufs_com_init(). Drop this entry completely. Signed-off-by:
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Dmitry Baryshkov authored
Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4. The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl) should use the 0x1a0 register, as stated in the downstream dtsi tree. Fixes: 2c91bf6b ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by:
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Kuogee Hsieh authored
Vdda regulators are related to both eDP and DP phy so that it should be managed at eDP and DP phy driver instead of controller. This patch removes vdda regulators related functions out of eDP/DP controller. Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1657038556-2231-4-git-send-email-quic_khsieh@quicinc.com Signed-off-by:
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Kuogee Hsieh authored
This patch add regulator_set_load() before enable regulator at DP phy driver. Signed-off-by:
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Kuogee Hsieh authored
This patch add regulator_set_load() before enable regulator at eDP phy driver. Signed-off-by:
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- Jul 05, 2022
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Neil Armstrong authored
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY used to communicate with DSI panels. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220705075650.3165348-3-narmstrong@baylibre.com Signed-off-by:
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Neil Armstrong authored
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY to communicate with DSI panels, this adds the bindings. This Analog D-PHY works with a separate Digital MIPI D-PHY. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220705075650.3165348-2-narmstrong@baylibre.com Signed-off-by:
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Jiang Jian authored
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/phy/broadcom/phy-brcm-usb-init.c line: 864 * Make sure the the second and third memory controller changed to * Make sure the second and third memory controller Signed-off-by:
Jiang Jian <jiangjian@cdjrlc.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220621122401.115500-1-jiangjian@cdjrlc.com Signed-off-by:
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Peter Geis authored
The initial otg state for the phy defaults to device mode. The actual state isn't detected until an ID IRQ fires. Fix this by syncing the ID state during initialization. Fixes: 51a9b2c0 ("phy: rockchip-inno-usb2: Handle ID IRQ") Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Reviewed-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com Signed-off-by:
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Robert Marko authored
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, so add the support for the Gen3 one. It uses the same register layout as IPQ6018. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Robert Marko authored
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, document the bindings for the Gen3 one. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220621195512.1760362-2-robimarko@gmail.com Signed-off-by:
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Robert Marko authored
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz like every other PCIe QMP PHY does, so make it configurable as part of the qmp_phy_cfg. Signed-off-by:
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Johan Hovold authored
Use lower case hex consistently for define values. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
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Johan Hovold authored
Clean up the QMP defines by removing some stray white space and making sure values are aligned. Signed-off-by:
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Johan Hovold authored
Clean up the QMP v4 and v5 defines by moving a few entries that were out of order. Signed-off-by:
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