- Aug 24, 2023
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Ville Syrjälä authored
port_clock is what the encoder/dpll code is supposed to calculate, it is not the input clock. Use the dotclock as the target we're trying to achieve instead. TODO: the SDVO TV clocking is a mess atm and needs further work Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230705202122.17915-7-ville.syrjala@linux.intel.com Acked-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Call *_calc_dpll_params() even in cases where the encoder has computed the DPLL params for us. The SDVO TV output code doesn't populate crtc_state->dpll.dot leading to the dotclock getting calculated as zero, and that leads to all kinds of real problems. The g4x DP code also doesn't populate the derived dividers nor .vco, which could also create some confusion. Signed-off-by:
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Ville Syrjälä authored
Allow *_calc_dpll_params() to be called even if the N/P dividers are zero without warning. We'll want to call these to make sure the derived values are fully computed, but not all users (VLV DSI in particular) even enable the DPLL and thus the dividers will be left at zero. It could also be possible that the BIOS has misprogrammed the DPLL (IIRC happened with some SNB machines with 4k+ displays) and thus we'll currently generate a lot of dmesg spew. Better be silent and just let the normal state checker/etc. deal with any driver bugs. Signed-off-by:
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Ville Syrjälä authored
The SDVO inputs are reported a simple number, not a bitmask. Adjust the code to match reality. Note that we don't actually support dual input SDVO devices, and we just always use the first input. Signed-off-by:
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Ville Syrjälä authored
Put parens around macro argument evaluation for safety. Signed-off-by:
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Ville Syrjälä authored
I have at least one SDVO device (some Lenovo DVI-I ADD2 card, based on Conexant CX25904) where GetAttachedDisplays returns success but fails to report any attached displays unless we precede the command with a SetTargetOutput. Make it so. I wasn't able to spot anything in the SDVO spec stating that this should be necessary, but real world wins over spec. Signed-off-by:
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Juha-Pekka Heikkila authored
Add missing spin_lock/unlock Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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Imre Deak authored
After the commit in the Fixes: line below, HPD polling stopped working on i915, since after that change calling drm_kms_helper_poll_enable() doesn't restart drm_mode_config::output_poll_work if the work was stopped (no connectors needing polling) and enabling polling for a connector (during runtime suspend or detecting an HPD IRQ storm). After the above change calling drm_kms_helper_poll_enable() is a nop after it's been called already and polling for some connectors was disabled/re-enabled. Fix this by calling drm_kms_helper_poll_reschedule() added in the previous patch instead, which reschedules the work whenever expected. Fixes: d33a54e3 ("drm/probe_helper: sort out poll_running vs poll_enabled") CC: stable@vger.kernel.org # 6.4+ Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230822113015.41224-2-imre.deak@intel.com
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Imre Deak authored
Add a helper to reschedule drm_mode_config::output_poll_work after polling has been enabled for a connector (and needing a reschedule, since previously polling was disabled for all connectors and hence output_poll_work was not running). This is needed by the next patch fixing HPD polling on i915. CC: stable@vger.kernel.org # 6.4+ Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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- Aug 22, 2023
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Vinod Govindapillai authored
Combine all DP audio configs into a single function Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
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Vinod Govindapillai authored
The needed functionality can be performed using crtc_state here. Signed-off-by:
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Matt Roper authored
Most of the IS_METEORLAKE checks in the display code shouldn't actually be tied to MTL as a platform, but rather to the Xe_LPD+ display IP (which is used in MTL, but may show up again in future platforms). In cases where we're trying to match that specific IP, use a version check against IP_VER(14, 0). For cases where we're just handling new behavior introduced by this IP (but which may also be inherited by future IP as well), use a ver >= 14 check. The one exception here is the stolen memory workaround Wa_13010847436 (which is mislabelled as "Wa_22018444074" in the code). That's truly a MTL-specific issue rather than being tied to any of the IP blocks, so leaving the condition as IS_METEORLAKE is correct there. v2: - cdclk check should be >=, not >. (Gustavo) Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-19-matthew.d.roper@intel.com
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Matt Roper authored
Stepping-specific display behavior shouldn't be tied to MTL as a platform, but rather specifically to the Xe_LPD+ IP. Future non-MTL platforms may re-use this IP and will need to follow the exact same logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the display IP version. v2: - Rename macro to IS_DISPLAY_IP_STEP for consistency with the corresponding GT macro and handle steppings the same way. v3: - Drop the automatic "STEP_" pasting. v4: - Implement IS_DISPLAY_IP_STEP on top of IS_DISPLAY_IP_RANGE / IS_DISPLAY_STEP building blocks and make the parameters from/until instead of begin/fixed. (Jani) - Fix usage details in comment. v5: - Tweak macro comment. (Gustavo) Signed-off-by:
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Gustavo Sousa authored
That power domain became unused after commit 41b4c7fe ("drm/i915: Disable DC states for all commits"). Signed-off-by:
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- Aug 18, 2023
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Ankit Nautiyal authored
Currently for testing an output format with DSC, we just force the output format, without checking if it can be supported. This also creates an issue where there is a PCON which might need to convert from forced output format to the format to sink format. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-19-ankit.k.nautiyal@intel.com
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Ankit Nautiyal authored
Use checks for src and sink limits before computing compressed bpp for eDP. Signed-off-by:
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Ankit Nautiyal authored
Currently, we take the max lane, rate and pipe bpp, to get the maximum compressed bpp possible. We then set the output bpp to this value. This patch provides support to have max bpp, min rate and min lanes, that can support the min compressed bpp. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) -Fix the checks for limits->max/min_bpp while iterating over list of valid DSC bpcs. (Stan) v3: -Refactor the code to have pipe bpp/compressed bpp computation and slice count calculation separately for different cases. v4: -Separate the pipe_bpp calculation for eDP and DP. v5: -Get rid of magic numbers for max and min bpp, and improve documentation. (Stan). -Use functions for {src_sink}_{min_max}_compressed_bpp (Ville). v6: -Remove lines to set link config to max. v7: -Split the part to separate edp and dp functions for computing DSC BPP into separate patch. v8: -Separate mechanism to get compressed bpp for ICL,TGL and XELPD+. Signed-off-by: -
Ankit Nautiyal authored
Pull the code to get joiner constraints on maximum compressed bpp into separate function. Signed-off-by:
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Ankit Nautiyal authored
Currently we check if the pipe_bpp selected is >= the min DSC bpc/bpp requirement. We do not check if it is <= the max DSC bpc/bpp requirement. Add checks for max DSC BPC/BPP constraints while computing the pipe_bpp when DSC is in use. v2: Fix the commit message. Signed-off-by:
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Ankit Nautiyal authored
Refactor code to separate functions for eDP and DP for computing pipe_bpp/compressed bpp when DSC is involved. This will help to optimize the link configuration for DP later. v2: Fix checkpatch warning. Signed-off-by:
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Ankit Nautiyal authored
The helper intel_dp_dsc_compute_bpp gives the maximum pipe bpp that is allowed with DSC. Rename the this to reflect that it returns max pipe bpp supported with DSC. Signed-off-by:
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Ankit Nautiyal authored
To make way for fractional bpp support, avoid left shifting the output_bpp by 4 in helper intel_dp_dsc_get_output_bpp. Signed-off-by:
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Ankit Nautiyal authored
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24. Check this condition for cases where bpc is forced by debugfs flag dsc_force_bpc. If the check fails, then WARN and ignore the debugfs flag. For MST case the pipe_bpp is already computed (hardcoded to be 24), and this check is not required. Signed-off-by:
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Ankit Nautiyal authored
Separate out functions for getting maximum and minimum input BPC based on platforms, when DSC is used. v2: Use HAS_DSC macro instead of platform check while getting min input bpc. (Stan) Signed-off-by:
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Ankit Nautiyal authored
For MST the bpc is hardcoded to 8, and pipe bpp to 24. So avoid forcing DSC bpc for MST case. v2: Warn and ignore the debug flag than to bail out. (Jani) v3: Fix dbg message to mention forced bpc instead of bpp. v4: Fix checkpatch longline warning. Signed-off-by:
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Ankit Nautiyal authored
DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-8-ankit.k.nautiyal@intel.com
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Ankit Nautiyal authored
As per Bsepc:49259, Bigjoiner BW check puts restriction on the compressed bpp for a given CDCLK, pixelclock in cases where Bigjoiner + DSC are used. Currently compressed bpp is computed first, and it is ensured that the bpp will work at least with the max CDCLK freq. Since the CDCLK is computed later, lets account for Bigjoiner BW check while calculating Min CDCLK. v2: Use pixel clock in the bw calculations. (Ville) v3: Use helper to account for FEC overhead. (Stan) Signed-off-by:
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Ankit Nautiyal authored
In Bigjoiner check for DSC, bigjoiner interface bits for DP for DISPLAY > 13 is 36 (Bspec: 49259). v2: Corrected Display ver to 13. v3: Follow convention for conditional statement. (Ville) v4: Fix check for display ver. (Ville) v5: Added note for 2 PPC. (Stan) Signed-off-by:
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Ankit Nautiyal authored
Currently there are many places where we use output_bpp for link bpp and compressed bpp. Lets use consistent naming: output_bpp : The intermediate value taking into account the output_format chroma subsampling. compressed_bpp : target bpp for the DSC encoder. link_bpp : final bpp used in the link. For 444 sampling without DSC: link_bpp = output_bpp = pipe_bpp For 420 sampling without DSC: output_bpp = pipe_bpp / 2 link_bpp = output_bpp For 444 sampling with DSC: output_bpp = pipe_bpp link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in this case) For 420 sampling with DSC: output_bpp = pipe_bpp/2 link_bpp = compressed_bpp, computed with output_bpp Signed-off-by:
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Ankit Nautiyal authored
The final link bpp used to calculate the m_n values depend on the output_format. Though the output_format is set to RGB for MST case and the link bpp will be same as the pipe bpp, for the sake of semantics, lets calculate the m_n values with the link bpp, instead of pipe_bpp. Signed-off-by:
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Ankit Nautiyal authored
Move the check for limiting compressed bits_per_pixel for 420,422 formats in the helper to compute bits_per_pixel. v2: Fix typo in commit message. (Ankit) Signed-off-by:
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Ankit Nautiyal authored
While using DSC the compressed bpp is computed assuming RGB output format. Consider the output_format and compute the compressed bpp during mode valid and compute config steps. For DP-MST we currently use RGB output format only, so continue using RGB while computing compressed bpp for MST case. v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville) Signed-off-by:
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Matt Roper authored
We don't really need a feature flag for has_4tile since there's a well-defined cutover point (DG2) at which all new platforms started using Tile4 as their Y-major tiling layout. The GT side of the code already handles Tile4 vs legacy TileY with checks on the IP version rather than looking at the feature flag, and we can simplify the display code similarly (which will also make it more self-contained for re-use in the Xe driver). Signed-off-by:
Haridhar Kalvala <haridhar.kalvala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230810234618.3738870-4-matthew.d.roper@intel.com
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Matt Roper authored
Rather than picking random tiling formats from a pool that contains both TileY and Tile4 and then trying to replace one with the other depending on the platform, it's simpler to just use a single enum value that represents whatever the platform-appropriate Y-major tiling format is (i.e., Tile4 on Xe_HP and beyond, legacy TileY on earlier platforms). Signed-off-by:
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Matt Roper authored
All production DG2 cards have display stepping C0 or later. We can drop Wa_14013215631 (only applies to pre-C0) and make Wa_14010547955 unconditional (applies to everything B0 and beyond). Also drop the now-unused IS_DG2_DISPLAY_STEP macro. Bspec: 44477 Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230816214201.534095-9-matthew.d.roper@intel.com
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Matt Roper authored
The first production SoC steppings for DG2 were C0 (for G10), B1 (for G11), and A1 (for G12). This corresponds to PCI revision IDs 0x8, 0x5, and 0x1 respectively. Add this information to the driver's pre-production detection. Bspec: 44477 Signed-off-by:
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Gustavo Sousa authored
According to the BSpec, voltage swing programming should be done for owned PHY lanes. Do not program a not-owned PHY lane. BSpec: 74103, 74104 Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Gustavo Sousa authored
Display must not enable or disable transmitters for not-owned PHY lanes. BSpec: 64539 Reviewed-by:
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Gustavo Sousa authored
It is possible to generalize the "disable" value for the transmitters to be a bit mask based on the port width and the port reversal boolean, with a small exception for DP-alt mode with "x1" port width. Simplify the code by using such a mask and a for-loop instead of using switch-case statements. v2: - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection. (Jani) BSpec: 64539 Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: -
Gustavo Sousa authored
There are more parts of C10/C20 programming that need to take owned lanes into account. Define the function intel_cx0_get_owned_lane_mask() and use it. There will be new users of that function in upcoming changes. BSpec: 64539 Reviewed-by:
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