- Jun 29, 2017
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Ken Ma authored
If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by:
Ken Ma <make@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Stefan Wahren authored
We get a warning during boot with enabled EARLY_PRINTK that we try to set a irq_chip without data. This is caused by ignoring the return value of irq_of_parse_and_map(). So avoid calling gpiochip_set_chained_irqchip() in error case. Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Fixes: 85ae9e51 ("pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP") Signed-off-by:
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- Jun 26, 2017
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Bjorn Andersson authored
Document the maintainership of the Qualcomm pinctrl drivers to improve the hitrate. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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- Jun 20, 2017
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Mauro Carvalho Chehab authored
As pinctrl describes a feature from drivers/base, place it at the right book. Signed-off-by:
Mauro Carvalho Chehab <mchehab@s-opensource.com> Signed-off-by:
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Dan Carpenter authored
devm_pinctrl_register() returns error pointers, it doesn't return NULL. Fixes: b5c23aa4 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Masahiro Yamada authored
The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 336306ee ("pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driver") Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show(). Filling non-existing ports with '-1' turned out a bad idea. Fixes: 70f2f9c4 ("pinctrl: uniphier: add UniPhier PH1-LD11 pinctrl driver") Signed-off-by:
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Linus Walleij authored
Merge tag 'samsung-pinctrl-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers update for v4.13: 1. Split drivers per ARMv7 and ARMv8 architectures because there is no need to compile everything on each of them. 2. Fix for possible NULL-pointer dereference after memory allocation failure. 3. Cleanups (silencing cast warnings, constify, removal of unneeded casts, removal of modular boiler-plate).
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- Jun 16, 2017
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Hanna Hawa authored
This commit adds a pinctrl driver for the CP110 part of the Marvell Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all the MPP pins are available. On the other side, the Armada 8K has two CP110, and the available MPPs are split between the master CP110 (MPPs 32 to 62) and the slave CP110 (MPPs 0 to 31). The register interface to control the MPPs is however the same as all other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic. Signed-off-by:
Hanna Hawa <hannah@marvell.com> Reviewed-by:
Shadi Ammouri <shadi@marvell.com> [updated for mvebu pinctrl and 4.9 changes: - converted to simple_mmio - converted to syscon/regmap - removed unimplemented .remove function - dropped DTS changes - defered gpio ranges to DT - fixed warning - properly set soc->nmodes -- rmk] Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> [ add missing MPP[61:56] function 14 (SDIO) -- Konstantin Porotchkin] Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> [ allow to properly register more then one instance of this driver -- Grzegorz Jaszczyk] Signed-off-by:
Grzegorz Jaszczyk <jaz@semihalf.com> [ - rebased on 4.12-rc1 - fixed the 80 character limit for mvebu_mpp_mode array - aligned the compatible name on the ones already used - fixed the MPP table for CP110: some MPP are not available on Armada 7K -- Gregory CLEMENT] Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Hanna Hawa authored
This commit adds a pinctrl driver for the pin-muxing controller found in the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register interface is compatible with the one used by previous mvebu pin controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c is used. Signed-off-by:
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Russell King authored
Armada 8040 also needs orion pinctrl, and as these symbols are only selected, there's no need to make them depend on PLAT_ORION. Reviewed-by:
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Gregory CLEMENT authored
The offset property of the pinctrl node, when a regmap is used in the device tree, was never used nor documented in the binding. Moreover, the compatible string is enough to let the driver know which offset using. So this patch removes the property and move the information at the driver level. Reviewed-by:
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Jerome Brunet authored
Add Tsin A pins to bank DV and X. We don't have a driver for the tsin yet but since the tsin A pinmux is enabled by default at boot time, declaring this pinmux is required to properly operate on GPIOX. Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output as the tsin A seems to have priority. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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- Jun 09, 2017
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Mika Westerberg authored
This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
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Mika Westerberg authored
On some SoCs not all pins in a group use the same mode when a certain function is muxed out of them. This makes it possible to specify mode per pin as an array instead in addition to single integer. Signed-off-by:
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Mika Westerberg authored
The Intel GPIO hardware has a concept of pad groups, which means 1 to 32 pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The existing hardware has the same amount of pads in each pad group (except the last one) so it is possible to use community->gpp_size to calculate start offset of each register. With the next generation SoCs the pad group size is not always the same anymore which means we cannot use community->gpp_size for register offset calculations directly. To support variable size pad groups we introduce struct intel_padgroup that can be filled in by the client drivers according the hardware pad group layout. The core driver will always use these when it performs calculations for pad register offsets. The core driver will automatically populate pad groups based on community->gpp_size if the driver does not provide any. This makes sure the existing drivers still work as expected. Signed-off-by:
Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by:
Tan Jui Nee <jui.nee.tan@intel.com> Reviewed-by:
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Chen-Yu Tsai authored
The R_PIO on the A83T is almost the same as the one found on the A64, except that the CIR_RX function was moved from pin PL11 to pin PL12. Add a driver for it. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Chen-Yu Tsai authored
The R_PIO on the A83T is almost the same as the one found on the A64, except that the CIR_RX function was moved from pin PL11 to pin PL12. Add a compatible string for it. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Scott Branden authored
Use consistent license headers for Broadcom files by placing additional comments outside of standard legal header. Also, update legal header to 2017 format as "Broadcom Corporation" has changed to "Broadcom". Signed-off-by:
Scott Branden <scott.branden@broadcom.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Tobias Klauser authored
struct irq_domain_ops is not modified, so it can be made const. Suggested-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Tobias Klauser <tklauser@distanz.ch> Acked-by:
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Alexandre TORGUE authored
There is no link between the number of elements of tab which contains all pin desc (located in each pinctrl-stm32xxxx.c files) and the pin number (defined in the tab). Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
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Jerome Brunet authored
Add GPIO interrupt information to pinctrl data. Added to the original version from Jerome was data for Meson GXL. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Acked-by:
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Heiner Kallweit authored
After commit 34e61801 "pinctrl: meson-gxbb: Add missing GPIODV_18 pin entry" I started to get the following warning: "meson-pinctrl c8834000.periphs:pinctrl@4b0: names 119 do not match number of GPIOs 120" It turned out that not the mentioned commit has a problem, it just revealed another problem which had existed before. There is no PIN GPIOX_22 on Meson GXBB. Fixes: 468c234f ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC") Signed-off-by:
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- Jun 08, 2017
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Krzysztof Kozlowski authored
For S5Pv210 retention control, the driver stores the iomem pointer from of_iomap() under a void pointer member. This makes sparse unhappy: drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: warning: incorrect type in argument 1 (different address spaces) drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: expected void const volatile [noderef] <asn:2>*addr drivers/pinctrl/samsung/pinctrl-exynos.c:664:36: got void * The iomem pointer is used safely (stored under priv by s5pv210_retention_init(), used by s5pv210_retention_disable()) thus we can add explicit casts to iomem to silence the warning. Signed-off-by:Krzysztof Kozlowski <krzk@kernel.org>
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Krzysztof Kozlowski authored
Check if kmemdup failed during wakeup banks initialization. Otherwise NULL pointer would be stored under "irq_chip" member of bank and later dereferenced in interrupt handler. Signed-off-by: -
Krzysztof Kozlowski authored
Static exynos_irq_chip structures, containing driver specific data, are referenced only through opaque data pointer in const of_device_id table. The contents of pointed memory (exynos_irq_chip structure itself) is then copied with kmemdup() during wakeup initialization so exynos_irq_chip can be made const for code safenes. Signed-off-by: -
Krzysztof Kozlowski authored
Exynos pinctrl drivers contain pretty big per-SoC data structures. The pinctrl-exynos object file contained code and data for both ARMv7 and ARMv8 SoCs thus it grew big. There will not be a shared image between ARMv7 and ARMv8 so there is no need to combine all of this into one driver. Splitting the data allows to make it more granular (e.g. code related to ARMv8 Exynos is self-contained), slightly speed up the compilation and reduce the effective size of compiled kernel. The common data structures and functions reside still in existing pinctrl-exynos.c. Only the SoC-specific parts were moved out to new files. Except marking few functions non-static and adding them to header, there were no functional changes in the code. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Acked-by:
Alim Akhtar <alim.akhtar@samsung.com> Tested-by:
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- May 31, 2017
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.13 - Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W, - Add support for RZ/G1M and RZ/G1E, - Small fixes and cleanups.
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Alexandre TORGUE authored
Add .get_direction() gpiochip callback in STM32 pinctrl driver. Signed-off-by:
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Alexandre TORGUE authored
This patch ensures that pin is correctly set as gpio input when it is used as an interrupt. Signed-off-by:
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Arnd Bergmann authored
With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver, which then results in a link failure: drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0': :(.text+0x7910): undefined reference to `__devm_regmap_init_i2c' drivers/pinctrl/built-in.o: In function `mcp23s08_init': :(.init.text+0x110): undefined reference to `i2c_register_driver' drivers/pinctrl/built-in.o: In function `mcp23s08_exit': :(.exit.text+0x3c): undefined reference to `i2c_del_driver' To avoid the problem, this adds another dependency on I2C that enforces mcp23s08 to be a loadable module whenever the I2C core is a module. Fixes: 64ac43e6 ("gpio: mcp23s08: move to pinctrl") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by:
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- May 30, 2017
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Martin Schiller authored
Signed-off-by:
Martin Schiller <ms@dev.tdt.de> Signed-off-by:
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Icenowy Zheng authored
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs (especially A20), and can use modified version of the A10/A20 pinctrl driver. Add a compatible string for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
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Icenowy Zheng authored
As we added A20 support to A10 pinctrl driver, now we can delete the dedicated A20 pinctrl driver, which is duplicated code. Signed-off-by:
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Icenowy Zheng authored
As A20 is designed as a pin-compatible upgrade of A10, their pin controller are very similar, and can share one driver. Add A20 support to the A10 driver. Signed-off-by:
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Icenowy Zheng authored
Allwinner A10, A20 and R40 SoCs have similar GPIO layout. Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support into A10 driver, and add R40 support into it. Signed-off-by:
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- May 29, 2017
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David Wu authored
There are 2 IP blocks pin routes need to be switched, that are uart2dbg, pcie_clkreq. Signed-off-by:
David Wu <david.wu@rock-chips.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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David Wu authored
There are 8 IP blocks pin routes need to be switched, that are uart2dbg, gmac-m1-optimized, pdm, spi, i2s2, card, tsp, cif. Signed-off-by:
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David Wu authored
There are 9 IP blocks pin routes need to be switched, that are pwm-0, pwm-1, pwm-2, pwm-3, sdio, spi, emmc, uart2, uart1. Signed-off-by:
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David Wu authored
On the some rockchip SOCS, some things like rk3399 specific uart2 can use multiple pins. Somewhere between the pin io-cells and the uart it seems to have some sort of switch to decide to which pin to actually route the data. +-------+ +--------+ /- GPIO4_B0 (pinmux 2) | uart2 | -- | switch | --- GPIO4_C0 (pinmux 2) +-------+ +--------+ \- GPIO4_C3 (pinmux 2) (switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1]) The routing switch is determined by one pin of a specific group to be set to its special pinmux function. If the pinmux setting is wrong for that pin the ip block won't work correctly anyway. Signed-off-by:
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