- Jan 10, 2023
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Mario Limonciello authored
Add an early_init phase to MES for fetching and validating microcode from the filesystem. If MES microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for MES microcode into the early_init phase so that if it's not available, early_init will fail. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Yang Li authored
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:7431:3-4: Unneeded semicolon ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:7485:4-5: Unneeded semicolon ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:7489:3-4: Unneeded semicolon Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3635 Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Yi Yang authored
Smatch report warning as follows: Line 53679: drivers/gpu/drm/amd/display/dc/core/dc_stream.c:402 dc_stream_set_cursor_position() warn: variable dereferenced before check 'stream' The value of 'dc' has been assigned after check whether 'stream' is NULL. Fix it by remove redundant assignment. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Yi Yang <yiyang13@huawei.com> Signed-off-by:
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Hamza Mahfooz authored
Currently, there are issues with enabling PSR-SU + DSC. This stems from the fact that DSC imposes a slice height on transmitted video data and we are not conforming to that slice height in PSR-SU regions. So, pass slice_height into su_y_granularity to feed the DSC slice height into PSR-SU code. Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Mario Limonciello authored
Simplifies the code so that all VCN versions will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Reviewed-by:
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Mario Limonciello authored
The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry. Reviewed-by:
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Mario Limonciello authored
When firmware is missing we get failures at every step. ``` [ 3.855086] amdgpu 0000:04:00.0: Direct firmware load for amdgpu/green_sardine_sdma.bin failed with error -2 [ 3.855087] [drm:amdgpu_sdma_init_microcode [amdgpu]] *ERROR* SDMA: Failed to init firmware "amdgpu/green_sardine_sdma.bin" [ 3.855398] [drm:sdma_v4_0_early_init [amdgpu]] *ERROR* Failed to load sdma firmware! ``` Realistically we don't need all of these, a user can tell from the first one that request_firmware emitted what happened. Drop the others. Reviewed-by:
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Mario Limonciello authored
Simplifies the code so that all SDMA versions will get the firmware name from `amdgpu_ucode_ip_version_decode`. v2: squash in fix from Srinivasan Reviewed-by:
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Mario Limonciello authored
The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. Reviewed-by:
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Mario Limonciello authored
All microcode runs a basic validation after it's been loaded. Each IP block as part of init will run both. Introduce a wrapper for request_firmware and amdgpu_ucode_validate. This wrapper will also remap any error codes from request_firmware to -ENODEV. This is so that early_init will fail if firmware couldn't be loaded instead of the IP block being disabled. Reviewed-by:
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Mario Limonciello authored
The special case for the one dGPU has been moved into `amdgpu_ucode_ip_version_decode`, so simplify this code. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Mario Limonciello authored
Remove the special casing from SMU v11 code. No intended functional changes. Signed-off-by:
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Mario Limonciello authored
This will allow other parts of the driver that currently special case firmware file names to before IP version style naming to just have a single call to `amdgpu_ucode_ip_version_decode`. Signed-off-by:
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Mario Limonciello authored
Removing the firmware framebuffer from the driver means that even if the driver doesn't support the IP blocks in a GPU it will no longer be functional after the driver fails to initialize. This change will ensure that unsupported IP blocks at least cause the driver to work with the EFI framebuffer. Cc: stable@vger.kernel.org Suggested-by:
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Luben Tuikov authored
Fix potential NULL dereference, in the case when "man", the resource manager might be NULL, when/if we print debug information. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Cc: Dan Carpenter <error27@gmail.com> Cc: kernel test robot <lkp@intel.com> Fixes: 7554886d ("drm/amdgpu: Fix size validation for non-exclusive domains (v4)") Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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- Jan 06, 2023
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Aaron Liu authored
1. Rename securedisplay_cmd to ta_securedisplay_cmd. 2. Rename ta_securedisplay_max_phy to ta_securedisplay_phy_ID. 3. update securedisplay_cmd to ta_securedisplay_cmd Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
Shane Xiao <shane.xiao@amd.com> Reviewed-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
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Evan Quan authored
Then we are able to set a new ppt limit via the hwmon interface(power1_cap). Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Correct the reference clock as 25Mhz for SMU13 fan speed calculation. Signed-off-by:
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Praful Swarnakar authored
[Why & How] Remove redundant log in DSC that just add additional blank prints Signed-off-by:
Praful Swarnakar <praful.swarnakar@amd.com> Signed-off-by:
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Wen Yang authored
The following errors occurred when using gcc 7.5.0-3ubuntu1~18.04: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function ‘dc_stream_remove_writeback’: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:543:55: warning: array subscript is above array bounds [-Warray-bounds] stream->writeback_info[j] = stream->writeback_info[i]; ~~~~~~~~~~~~~~~~~~~~~~^~~ Add a check to make sure that num_wb_info won't overflowing the writeback_info buffer. Fixes: 6fbefb84 ("drm/amd/display: Add DC core changes for DCN2") Signed-off-by:
Wen Yang <wenyang.linux@foxmail.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Alexey Kodanev authored
pipe_ctx pointer cannot be NULL when getting the address of an element of the pipe_ctx array. Moreover, the MAX_PIPES is defined as 6, so pipe_ctx is not NULL after the loop either. Detected using the static analysis tool - Svace. Signed-off-by:
Alexey Kodanev <aleksei.kodanev@bell-sw.com> Signed-off-by:
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Hawking Zhang authored
amdgpu_ras_block_late_init will be invoked in IP specific ras_late_init call as a common helper for all the IP blocks. However, when amdgpu_ras_block_late_init call amdgpu_ras_query_error_count to query ras error counters, amdgpu_ras_query_error_count queries all the IP blocks that support ras query interface. This results to wrong error counters cached in software copies when there are ras errors detected at time zero or warm reset procedure. i.e., in sdma_ras_late_init phase, it counts on sdma/mmhub errors, while, in mmhub_ras_late_init phase, it still counts on sdma/mmhub errors. The change updates amdgpu_ras_query_error_count interface to allow query specific ip error counter. It introduces a new input parameter: query_info. if query_info is NULL, it means query all the IP blocks, otherwise, only query the ip block specified by query_info. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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xurui authored
HPD signals on DVI ports can be fired off before the pins required for DDC probing actually make contact, due to the pins for HPD making contact first. This results in a HPD signal being asserted but DDC probing failing, resulting in hotplugging occasionally failing. Rescheduling the hotplug work for a second when we run into an HPD signal with a failing DDC probe usually gives enough time for the rest of the connector's pins to make contact, and fixes this issue. Signed-off-by:
xurui <xurui@kylinos.cn> Signed-off-by:
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Alex Deucher authored
A number of the gfx8 cases were the same. Clean them up. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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- Jan 04, 2023
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Randy Dunlap authored
Fix all kernel-doc warnings in dc/core/dc.c: dc.c:385: warning: missing initial short description on line: * dc_stream_adjust_vmin_vmax: dc.c:392: warning: contents before sections dc.c:399: warning: No description found for return value of 'dc_stream_adjust_vmin_vmax' dc.c:434: warning: Excess function parameter 'adjust' description in 'dc_stream_get_last_used_drr_vtotal' dc.c:434: warning: No description found for return value of 'dc_stream_get_last_used_drr_vtotal' dc.c:574: warning: No description found for return value of 'dc_stream_configure_crc' dc.c:1746: warning: No description found for return value of 'dc_commit_state_no_check' dc.c:4991: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * dc_extended_blank_supported 0 Decide whether extended blank is supported dc.c:4991: warning: missing initial short description on line: * dc_extended_blank_supported 0 Decide whether extended blank is supported dc.c:4723: warning: Function parameter or member 'dc' not described in 'dc_enable_dmub_outbox' dc.c:4926: warning: Function parameter or member 'dc' not described in 'dc_process_dmub_dpia_hpd_int_enable' dc.c:4926: warning: Function parameter or member 'hpd_int_enable' not described in 'dc_process_dmub_dpia_hpd_int_enable' 12 warnings Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Reported-by:
kernel test robot <lkp@intel.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: amd-gfx@lists.freedesktop.org Signed-off-by:
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Michel Dänzer authored
This reverts commit de05abe6. The bug referenced below was bisected to this commit. There has been no activity toward fixing it in 3 months, so let's revert for now. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2162 Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Jiapeng Chong authored
The function dmub_outbox_irq_info_funcs is defined in the irq_service_dcn201.c file, but not called elsewhere, so remove this unused function. drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:139:43: warning: unused variable 'dmub_outbox_irq_info_funcs'. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3520 Reported-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We skip dsc_validation on pipes that are underlays, but in the acquire_dsc code we don't have this check. In certain conditions (when underlay pipe index is lower) we will assign the dsc resource to the underlay pipe and skip the base pipe. Now during dsc_validation we will skip the underlay pipe (this has the dsc resource) but try to validate the base pipe(this doesn't have a dsc resource) due to this mismatch we hit a NULLPTR [How] In the acquire_dsc add a check for underlay pipe so we don't acquire a dsc resource for this pipe. This will match the acquire/validation conditions. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Hersen Wu <Hersenxs.Wu@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Stanley.Yang authored
[Why] [ 41.285804] RIP: 0010:amdgpu_ras_feature_enable+0x15c/0x310 [amdgpu] [ 41.285945] Code: 48 89 c1 48 c7 c2 b9 f2 88 c1 48 c7 c0 c0 f2 88 c1 49 8b 3c 24 48 0f 44 d0 48 c7 c6 98 33 80 c1 e8 5f 52 75 d9 e9 fa fe ff ff <0f> 0b e9 66 ff ff ff 48 8b 3d 86 8c 0f da ba 00 04 00 00 be c0 0d [ 41.285946] RSP: 0018:ffffbccdc72efc90 EFLAGS: 00010246 [ 41.285948] RAX: 0000000000000004 RBX: ffff931897406980 RCX: 0000000000000002 [ 41.285949] RDX: 0000000000000dc0 RSI: 0000000000000002 RDI: ffff931500042b00 [ 41.285950] RBP: ffffbccdc72efcc0 R08: 0000000000000002 R09: ffff931885b87000 [ 41.285951] R10: 0000000000ffff10 R11: 0000000000000001 R12: ffff931893e20000 [ 41.285952] R13: 0000000000000001 R14: ffff931885b87000 R15: 0000000000000000 [ 41.285953] FS: 0000000000000000(0000) GS:ffff931c6f200000(0000) knlGS:0000000000000000 [ 41.285954] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 41.285955] CR2: 000055dd6f532008 CR3: 000000061b010006 CR4: 00000000003706e0 [ 41.285956] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 41.285957] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 41.285958] Call Trace: [ 41.285959] <TASK> [ 41.285963] ? gfx_v11_0_early_init+0x250/0x250 [amdgpu] [ 41.286117] gfx_v11_0_late_init+0x8c/0xb0 [amdgpu] [ 41.286271] amdgpu_device_ip_late_init+0x8d/0x3c0 [amdgpu] [ 41.286401] amdgpu_device_init.cold+0x1677/0x1fda [amdgpu] [ 41.286616] ? pci_bus_read_config_word+0x4a/0x70 [ 41.286621] ? do_pci_enable_device+0xdb/0x110 [ 41.286625] amdgpu_driver_load_kms+0x1a/0x160 [amdgpu] [ 41.286762] amdgpu_pci_probe+0x18d/0x3a0 [amdgpu] [ 41.286898] local_pci_probe+0x4b/0x90 [ 41.286901] work_for_cpu_fn+0x1a/0x30 [ 41.286903] process_one_work+0x22b/0x3d0 [ 41.286905] worker_thread+0x223/0x420 [ 41.286907] ? process_one_work+0x3d0/0x3d0 [ 41.286908] kthread+0x12a/0x150 [ 41.286911] ? set_kthread_struct+0x50/0x50 [ 41.286913] ret_from_fork+0x22/0x30 [How] For specific asic, only mem ecc is enabled, sram ecc is not enabled, but it still need to send ras enable cmd to gfx block to support poison mode, so add check posion mode. Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Stanley.Yang authored
For GFX 11.0.3, Due to security policy, there is no way to check UcFatalEn field of UMCCH0_0_GeccCtrl to identify UMC poison mode. This is workaround force set umc poison mode as 1 for GFX 11.0.3 Signed-off-by:
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Aric Cyr authored
Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aric Cyr authored
[why & how] By moving bw_ctx field to the end of the dc_state the state can be cleared more efficiently without resulting in large DML memcpy operations, resulting in better mode enumeration performance on some platforms. Acked-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Tested-by:
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Leo Chen authored
[Why & How] For certain features, there will be more implementations needed in the if-block. Braces are added as part of the preparation. Acked-by:
Leo Chen <sancchen@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] ignore_msa_timing_param is used by SubVP logic to determine if SubVP + DRR is possible. Linux does not support freesync on multi display config, which results in incorrect assumption of VRR support if we set this parameter when VRR is supported, but not enabled. Signed-off-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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Wenjing Liu authored
[why] During DP2.1 LL CTS if test equipment requests to change between DP2.1 and DP1.4 link rates, we need to swap between HPO and DIO encoders by remapping encoder resource. [how] Add a function dc resource to update encoder resources and toggle dpms state for all enabled stream associated witht the link under test. Acked-by:
Jun Lei <Jun.Lei@amd.com> Tested-by:
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Wenjing Liu authored
[why] Pixel rate div depends on the type of encoder that we are enabling stream with. If we swap between HPO and DIO encoder at the time we call enable stream for the new encoder, we must reprogram pixel rate div based on the new encoder type. Acked-by:
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Wenjing Liu authored
[why] dccg clock programming shouldn't be part of link hwss programming sequence. The scope of link hwss is limited to encoder and phy programming. Acked-by:
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Dmytro Laktyushkin authored
This function is meant to be used on multi-edp systems and only makes sense if only links with connected panels are considered. Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] On some monitors we see a brief flash of corruption during the monitor disable sequence caused by FIFO being disabled in the middle of an active DP stream. [How] Wait until DP vid stream is disabled before turning off the FIFO. The FIFO reset on DP unblank should take care of clearing any FIFO error, if any. Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Syed Hassan <Syed.Hassan@amd.com> Tested-by:
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Swapnil Patel authored
[Why] DCN301 resource function is missing function pointer to handle cases with unknown plane state. This causes assertion when global state is validated while using swizzle parameter as “DC_UNKNOWN” [How] Add function pointer to handle and patch cases when plane state is unknown. Acked-by:
Swapnil Patel <Swapnil.Patel@amd.com> Reviewed-by:
Sung joon Kim <Sungjoon.Kim@amd.com> Tested-by:
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