- Sep 26, 2020
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Guchun Chen authored
Merge ras sysfs creation together by calling sysfs_create_group once, as sysfs_update_group may not work properly as expected. v2: improve commit message Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tiecheng Zhou authored
In FLR routine, init_data_exchange is called at reset_sriov while fini_data_exchange is not. This will duplicating work thread. So call fini_data_exchange before reset for SRIOV Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Bokun Zhang authored
- Refactor the driver code to use amdgpu_virt_read_pf2vf_data and amdgpu_virt_write_vf2pf_data instead of writing all code in one function (which is the old amdgpu_virt_init_data_exchange) - Adding a new transaction method for VF2PF message between host and guest driver. Guest side will periodically update VF2PF message in the framebuffer. In the new header, we include guest ucode information, guest framebuffer usage, and engine usage - Clean up the old macros since they will cause compile error if the new transaction method is used v2: squash in build fix Signed-off-by:
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Bokun Zhang authored
- Update guest side VF2PF interface header file Signed-off-by:
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Ryan Taylor authored
Documents PP_FEATURE_MASK enum. Provides instructions on how to use ppfeaturemasks. v2: improve enum definitions and add kernel command line parameters to ppfeaturemask instructions v3: fix alignment issues Signed-off-by:Ryan Taylor <ryan.taylor@amd.com> Reviewed-by:
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John Clements authored
disable UMC RAS in lieu of stability issues on certain sku Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Alex Deucher authored
This allows us to set different defaults on a per asic basis. This way we can enable noretry on dGPUs where it can increase performance in certain cases and disable it on chips where it can be problematic. For now the default is 0 for all asics, but we may want to try and enable it again for newer dGPUs. Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Alex Deucher authored
This will allow us to have different defaults per asic in a future patch. Reviewed-by:
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Alex Deucher authored
Properly handle clang and older versions of gcc. Fixes: e77165bf ("drm/amd/display: Add DCN3 blocks to Makefile") Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Emily.Deng authored
Signed-off-by:
Emily.Deng <Emily.Deng@amd.com> Reviewed-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
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Jingwen Chen authored
smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid v3: directly skip psp fw loading in SRIOV Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
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Jingwen Chen authored
smc fw is not needed in SRIOV, thus driver should not try to get smc fw data. Signed-off-by:
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Flora Cui authored
max_caps might be 0, thus hdcp_work might be ZERO_SIZE_PTR Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Jiansong Chen authored
Remove gpu_info fw support for sienna_cichlid etc., since the information can be retrieved from discovery binary. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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- Sep 23, 2020
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Wang Qing authored
Modify the comment typo: "definately" -> "definitely". Signed-off-by:
Wang Qing <wangqing@vivo.com> Signed-off-by:
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Bernard Zhao authored
In the function dal_ddc_service_query_ddc_data, get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. This change is to make the code run a bit fast. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Changes since V1: *get rid of dal_ddc_i2c_payloads_destroy, call dal_vector_destruct() directly. Link for V1: *https://lore.kernel.org/patchwork/patch/1309014/ Signed-off-by:
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Bernard Zhao authored
Change the comment typo: "programm" -> "program". Signed-off-by:
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Bernard Zhao authored
Change the comment typo: "programm" -> "program". Signed-off-by:
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Ryan Taylor authored
Added IP block section to amdgpu.rst. Added more documentation to amd_ip_funcs. Created documentation for amd_ip_block_type. v2: Provides a more detailed DOC section on IP blocks v3: Clarifies the IP block list. Adds info on IP block enumeration. Signed-off-by:
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Stanley.Yang authored
mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Likun Gao authored
Update driver if file for sienna cichlid. Signed-off-by:
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Evan Quan authored
As this is already set inside the implementation of smu_set_watermarks_table(). Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
As they have no real dependence. And for Navi1x, the socclk/uclk dpms are enabled after DAL initialization. Signed-off-by:
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Evan Quan authored
Otherwise, that will be always true for Navi14. Signed-off-by:
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Stanley.Yang authored
GCEA/MMHUB EA error should not result to DF freeze, this is fixed in next generation, but for some reasons the GCEA/MMHUB EA error will result to DF freeze in previous generation, diver should avoid to indicate GCEA/MMHUB EA error as hw fatal error in kernel message by read GCEA/MMHUB err status registers. Changed from V1: make query_ras_error_status function more general make read mmhub er status register more friendly Changed from V2: move ras error status query function into do_recovery workqueue Changed from V3: remove useless code from V2, print GCEA error status instance number Signed-off-by: -
Sudheesh Mavila authored
SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM. Suggested-by:
Sudheesh Mavila <sudheesh.mavila@amd.com> Signed-off-by:
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Evan Quan authored
Different mclk dpm policy will be applied based on the VRAM width. Signed-off-by:
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Liu Shixin authored
Simplify the return expression. Signed-off-by:
Liu Shixin <liushixin2@huawei.com> Signed-off-by:
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Liu Shixin authored
Simplify the return expression. Signed-off-by:
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Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by:
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Qinglang Miao authored
Simplify the return expression. Signed-off-by:
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Lewis Huang authored
[Why] Update clock only when non-seamless boot stream exists creates regression on multiple scenerios. [How] Update clock in two conditions 1. Non-seamless boot stream exist. 2. Stream_count = 0 Fixes: 598c13b2 ("drm/amd/display: update clock when non-seamless boot stream exist") Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Qingqing Zhuo <Qingqing.zhuo@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Add new SCRATCH0 status bits for detecting restore state Signed-off-by:Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Chris Park authored
[Why] HDMI requires fallback to TMDS by redetection in order to switch PHY settings. This avoids black out when link training fail during mode setting, link quality update, disable driver sequence. [How] Allow driver to redetect HDMI displays based on retraining or fallback mechanism. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
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Taimur Hassan authored
[Why] When running a game/benchmark with v-sync disabled, disabling a plane (which is v-sync) can cause an underflow. This is due to flips that are pending before pipe locking being applied after locks are released and pipes have been re-arranged or disconnected. This can potentially apply a flip on the incorrect pipe. [How] Check that any pending flips are cleared before locking any pipes to ensure flips are applied on the correct pipes. Signed-off-by:
Taimur Hassan <syed.hassan@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] For DMUB implementation of PSR, the 'wait' parameter, used to determine if driver should wait for PSR enable/disable, is not implemented correctly. [How] Implement wait for PSR enable/disable. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Regression is caused by previous change with attempt to correct the extended cr aux rd interval delay due to mis interpretation of the DP specs. The change turns out not working well with certain RXs. So we decided to keep the cr aux rd interval logic as before. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Gary Li authored
[WHY] In DCN10 when a panel with YCbCr420 capability is connected via USB-C to HDMI active dongle, no YCbCr420 option is listed in Radeon settings. [HOW] Enable DP YCbCr420 mode support for DCN10 Signed-off-by:
Gary Li <gary.li@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] When disabling DP video, the current REG_WAIT timeout of 50ms is too low for certain cases with very high VSYNC intervals. [HOW] Increase the timeout to 102ms, so that refresh rates as low as 10Hz can be handled properly. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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